From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org,
qemu-s390x@nongnu.org, jcmvbkbc@gmail.com,
kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp,
gaosong@loongson.cn, jiaxun.yang@flygoat.com,
tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com,
edgar.iglesias@gmail.com
Subject: [PATCH 33/70] target/mips: Avoid tcg_const_* throughout
Date: Sun, 26 Feb 2023 19:41:56 -1000 [thread overview]
Message-ID: <20230227054233.390271-34-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org>
All remaining uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/mxu_translate.c | 4 +-
target/mips/tcg/translate.c | 56 +++++++++++------------
target/mips/tcg/tx79_translate.c | 4 +-
target/mips/tcg/micromips_translate.c.inc | 4 +-
target/mips/tcg/nanomips_translate.c.inc | 16 ++++---
5 files changed, 43 insertions(+), 41 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 8703b0cef4..bdd20709c0 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1072,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do half-word-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_const_i32(0);
+ TCGv_i32 t1 = tcg_constant_i32(0);
/* the left half-word first */
tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
@@ -1163,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do byte-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_const_i32(0);
+ TCGv_i32 t1 = tcg_constant_i32(0);
int32_t i;
/* the leftmost byte (byte 3) first */
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index bec0a26c83..7f1f12e0c7 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2099,14 +2099,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
- t1 = tcg_const_tl(pc_relative_pc(ctx));
+ t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
- t1 = tcg_const_tl(pc_relative_pc(ctx));
+ t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
gen_store_gpr(t0, rt);
@@ -2733,7 +2733,7 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc,
t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
- t1 = tcg_const_tl(0);
+ t1 = tcg_constant_tl(0);
t2 = tcg_temp_new();
gen_load_gpr(t2, rs);
switch (opc) {
@@ -3084,8 +3084,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_DIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3095,8 +3095,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_MODU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3175,16 +3175,16 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_DDIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
}
break;
case R6_OPC_DMODU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
}
@@ -3248,8 +3248,8 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
break;
case MMI_OPC_DIVU1:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3304,8 +3304,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
case OPC_DIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3355,8 +3355,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
case OPC_DDIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
@@ -4908,7 +4908,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_WSBH:
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0x00FF00FF);
+ TCGv t2 = tcg_constant_tl(0x00FF00FF);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_and_tl(t1, t1, t2);
@@ -4928,7 +4928,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSBH:
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
+ TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_and_tl(t1, t1, t2);
@@ -4940,7 +4940,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSHD:
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
+ TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
tcg_gen_shri_tl(t1, t0, 16);
tcg_gen_and_tl(t1, t1, t2);
@@ -8451,7 +8451,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 5:
case 6:
case 7:
- gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
+ gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel));
break;
default:
goto die;
@@ -9477,7 +9477,7 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
int fs)
{
- TCGv_i32 t1 = tcg_const_i32(0);
+ TCGv_i32 t1 = tcg_constant_i32(0);
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
TCGv_i32 fp2 = tcg_temp_new_i32();
@@ -9510,7 +9510,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
int fs)
{
- TCGv_i64 t1 = tcg_const_i64(0);
+ TCGv_i64 t1 = tcg_constant_i64(0);
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
TCGv_i64 fp2 = tcg_temp_new_i64();
@@ -11508,7 +11508,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
int16_t offset)
{
- TCGv_i32 t0 = tcg_const_i32(op);
+ TCGv_i32 t0 = tcg_constant_i32(op);
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
gen_helper_cache(cpu_env, t1, t0);
@@ -11852,7 +11852,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_PH_W:
check_dsp_r2(ctx);
{
- TCGv_i32 sa_t = tcg_const_i32(v2);
+ TCGv_i32 sa_t = tcg_constant_i32(v2);
gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
break;
@@ -11860,7 +11860,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_R_PH_W:
check_dsp_r2(ctx);
{
- TCGv_i32 sa_t = tcg_const_i32(v2);
+ TCGv_i32 sa_t = tcg_constant_i32(v2);
gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
break;
@@ -12049,14 +12049,14 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_QH_PW:
check_dsp_r2(ctx);
{
- TCGv_i32 ret_t = tcg_const_i32(ret);
+ TCGv_i32 ret_t = tcg_constant_i32(ret);
gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
break;
}
case OPC_PRECR_SRA_R_QH_PW:
check_dsp_r2(ctx);
{
- TCGv_i32 sa_v = tcg_const_i32(ret);
+ TCGv_i32 sa_v = tcg_constant_i32(ret);
gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
break;
}
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index d46bc73972..3a45a1bfea 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -243,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
return true;
}
- c0 = tcg_const_tl(0);
- c1 = tcg_const_tl(0xffffffff);
+ c0 = tcg_constant_tl(0);
+ c1 = tcg_constant_tl(0xffffffff);
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 23f80d4315..e8b193aeda 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
gen_base_offset_addr(ctx, t0, base, offset);
- t1 = tcg_const_tl(reglist);
- t2 = tcg_const_i32(ctx->mem_idx);
+ t1 = tcg_constant_tl(reglist);
+ t2 = tcg_constant_i32(ctx->mem_idx);
save_cpu_state(ctx, 1);
switch (opc) {
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index b3df7fec40..9398e28000 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -3359,7 +3359,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 0:
/* PRECR_SRA_PH_W */
{
- TCGv_i32 sa_t = tcg_const_i32(rd);
+ TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
@@ -3368,7 +3368,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 1:
/* PRECR_SRA_R_PH_W */
{
- TCGv_i32 sa_t = tcg_const_i32(rd);
+ TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
@@ -3864,10 +3864,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_nms(ctx);
if (rt != 0) {
TCGv t0 = tcg_temp_new();
- TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
- TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
- << 1);
- TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));
+ TCGv_i32 shift =
+ tcg_constant_i32(extract32(ctx->opcode, 0, 5));
+ TCGv_i32 shiftx =
+ tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1);
+ TCGv_i32 stripe =
+ tcg_constant_i32(extract32(ctx->opcode, 6, 1));
gen_load_gpr(t0, rs);
gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
@@ -4500,7 +4502,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
/* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) {
- TCGv tmp = tcg_const_tl(ctx->base.pc_next);
+ TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
generate_exception_end(ctx, EXCP_AdEL);
return 2;
--
2.34.1
next prev parent reply other threads:[~2023-02-27 8:21 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 5:41 [PATCH 00/70] tcg: Remove tcg_const_* Richard Henderson
2023-02-27 5:41 ` [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-06 13:54 ` Philippe Mathieu-Daudé
2023-03-06 13:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 02/70] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-02-27 5:41 ` [PATCH 03/70] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-06 14:00 ` Philippe Mathieu-Daudé
2023-03-06 19:20 ` Richard Henderson
2023-02-27 5:41 ` [PATCH 04/70] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-06 13:58 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 05/70] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
2023-02-27 5:41 ` [PATCH 06/70] target/arm: Improve trans_BFCI Richard Henderson
2023-02-27 5:41 ` [PATCH 07/70] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
2023-03-06 15:11 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 08/70] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-02-27 5:41 ` [PATCH 09/70] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-02-27 5:41 ` [PATCH 10/70] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2023-03-06 15:15 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 11/70] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-06 15:22 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 12/70] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
2023-03-06 13:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 13/70] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:49 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 14/70] target/cris: " Richard Henderson
2023-03-07 0:30 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 15/70] target/hexagon: Use tcg_constant_* for gen_constant_from_imm Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 17/70] target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 18/70] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 19/70] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 22:00 ` Richard Henderson
2023-02-27 22:38 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
2023-03-06 13:50 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 22/70] target/i386: Simplify POPF Richard Henderson
2023-02-27 9:04 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
2023-03-07 0:37 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 24/70] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
2023-02-27 5:41 ` [PATCH 25/70] target/m68k: Use tcg_constant_i32 " Richard Henderson
2023-03-06 14:14 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
2023-03-06 23:53 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
2023-03-07 0:03 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 23:59 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 29/70] target/microblaze: " Richard Henderson
2023-02-27 8:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 30/70] target/mips: Split out gen_lxl Richard Henderson
2023-03-06 13:31 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 31/70] target/mips: Split out gen_lxr Richard Henderson
2023-03-06 13:40 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
2023-03-06 13:41 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` Richard Henderson [this message]
2023-03-06 13:46 ` [PATCH 33/70] target/mips: Avoid tcg_const_* throughout Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 34/70] target/ppc: Split out gen_vx_vmul10 Richard Henderson
2023-03-06 15:08 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
2023-03-06 14:16 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 36/70] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-02-27 5:42 ` [PATCH 37/70] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 38/70] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-02-27 5:42 ` [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 40/70] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 41/70] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 42/70] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-02-27 5:42 ` [PATCH 43/70] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-02-27 5:42 ` [PATCH 44/70] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-02-27 5:42 ` [PATCH 45/70] target/riscv: Avoid tcg_const_* Richard Henderson
2023-02-27 9:05 ` Philippe Mathieu-Daudé
2023-03-06 13:53 ` liweiwei
2023-02-27 5:42 ` [PATCH 46/70] target/rx: Use tcg_gen_abs_i32 Richard Henderson
2023-03-06 13:48 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
2023-03-07 0:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
2023-03-06 14:18 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 49/70] target/rx: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:27 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 50/70] target/s390x: Split out gen_ri2 Richard Henderson
2023-02-27 9:09 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 51/70] target/s390x: Avoid tcg_const_i64 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 52/70] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
2023-03-07 0:23 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 53/70] target/sh4: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 54/70] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
2023-03-06 15:36 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32} Richard Henderson
2023-03-01 17:02 ` Mark Cave-Ayland
2023-03-06 15:37 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable Richard Henderson
2023-03-07 0:19 ` Philippe Mathieu-Daudé
2023-03-07 2:24 ` Richard Henderson
2023-03-07 10:20 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 57/70] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
2023-03-06 15:38 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 58/70] target/tricore: Use min/max for saturate Richard Henderson
2023-02-27 5:53 ` Richard Henderson
2023-02-27 5:42 ` [PATCH 59/70] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
2023-03-06 15:39 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 60/70] target/tricore: Drop some temp initialization Richard Henderson
2023-03-06 15:25 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 61/70] target/tricore: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:10 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 62/70] target/xtensa: Tidy translate_bb Richard Henderson
2023-02-27 9:19 ` Max Filippov
2023-03-07 0:07 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 63/70] target/xtensa: Tidy translate_clamps Richard Henderson
2023-02-27 9:22 ` Max Filippov
2023-03-07 0:24 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r Richard Henderson
2023-02-27 9:23 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll Richard Henderson
2023-02-27 9:26 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 66/70] target/xtensa: Split constant in bit shift Richard Henderson
2023-02-27 9:27 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 67/70] target/xtensa: Avoid tcg_const_i32 Richard Henderson
2023-02-27 9:31 ` Max Filippov
2023-03-07 0:06 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 68/70] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
2023-03-06 15:33 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 69/70] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-06 15:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 70/70] tcg: Drop tcg_const_* Richard Henderson
2023-03-06 15:30 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230227054233.390271-34-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=ale@rev.ng \
--cc=edgar.iglesias@gmail.com \
--cc=gaosong@loongson.cn \
--cc=jcmvbkbc@gmail.com \
--cc=jiaxun.yang@flygoat.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=mrolnik@gmail.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=tsimpson@quicinc.com \
--cc=ysato@users.sourceforge.jp \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).