From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org,
qemu-s390x@nongnu.org, jcmvbkbc@gmail.com,
kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp,
gaosong@loongson.cn, jiaxun.yang@flygoat.com,
tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com,
edgar.iglesias@gmail.com
Subject: [PATCH 05/70] target/arm: Create gen_set_rmode, gen_restore_rmode
Date: Sun, 26 Feb 2023 19:41:28 -1000 [thread overview]
Message-ID: <20230227054233.390271-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org>
Split out common subroutines for handing rounding mode
changes during translation. Use tcg_constant_i32 and
tcg_temp_new_i32 instead of tcg_const_i32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 17 ++++++++++++++
target/arm/translate-a64.c | 47 +++++++++++++++-----------------------
target/arm/translate-sve.c | 6 ++---
target/arm/translate-vfp.c | 26 ++++++++-------------
4 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 3dbff87349..062f91de54 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -616,6 +616,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
return ret;
}
+/*
+ * Set and reset rounding mode around another operation.
+ */
+static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
+{
+ TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
+ TCGv_i32 old = tcg_temp_new_i32();
+
+ gen_helper_set_rmode(old, new, fpst);
+ return old;
+}
+
+static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
+{
+ gen_helper_set_rmode(old, old, fpst);
+}
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 3c0462a9c1..9e682f36c9 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6146,13 +6146,12 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
{
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+ TCGv_i32 tcg_rmode;
+
fpst = fpstatus_ptr(FPST_FPCR_F16);
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(opcode & 7, fpst);
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
break;
}
case 0xe: /* FRINTX */
@@ -6231,10 +6230,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6304,10 +6302,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6944,9 +6941,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
rmode = FPROUNDING_TIEAWAY;
}
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
switch (type) {
case 1: /* float64 */
@@ -7023,7 +7018,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
g_assert_not_reached();
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -8771,9 +8766,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
assert(!(is_scalar && is_q));
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus);
fracbits = (16 << size) - immhb;
tcg_shift = tcg_constant_i32(fracbits);
@@ -8831,7 +8825,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
}
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
/* AdvSIMD scalar shift by immediate
@@ -10219,12 +10213,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
- tcg_rmode = NULL;
tcg_fpstatus = NULL;
+ tcg_rmode = NULL;
}
if (size == 3) {
@@ -10276,7 +10269,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12406,8 +12399,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_fpstatus = NULL;
}
if (rmode >= 0) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
}
@@ -12590,7 +12582,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
clear_vec_high(s, is_q, rd);
if (tcg_rmode) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12758,8 +12750,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (rmode >= 0) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
}
if (is_scalar) {
@@ -12859,7 +12850,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (tcg_rmode) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 3c65dd1ff2..3ca60fb36b 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4096,17 +4096,15 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- tmode = tcg_const_i32(arm_rmode_to_sf(mode));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
-
- gen_helper_set_rmode(tmode, tmode, status);
+ tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);
- gen_helper_set_rmode(tmode, tmode, status);
+ gen_restore_rmode(tmode, status);
return true;
}
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index e7acfb3338..dd782aacf4 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
fpst = fpstatus_ptr(FPST_FPCR);
}
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_op;
@@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
vfp_store_reg32(tcg_res, rd);
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
tcg_shift = tcg_constant_i32(0);
-
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_double, tcg_res;
@@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
vfp_store_reg32(tcg_res, rd);
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
}
--
2.34.1
next prev parent reply other threads:[~2023-02-27 8:19 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 5:41 [PATCH 00/70] tcg: Remove tcg_const_* Richard Henderson
2023-02-27 5:41 ` [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-06 13:54 ` Philippe Mathieu-Daudé
2023-03-06 13:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 02/70] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-02-27 5:41 ` [PATCH 03/70] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-06 14:00 ` Philippe Mathieu-Daudé
2023-03-06 19:20 ` Richard Henderson
2023-02-27 5:41 ` [PATCH 04/70] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-06 13:58 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` Richard Henderson [this message]
2023-02-27 5:41 ` [PATCH 06/70] target/arm: Improve trans_BFCI Richard Henderson
2023-02-27 5:41 ` [PATCH 07/70] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
2023-03-06 15:11 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 08/70] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-02-27 5:41 ` [PATCH 09/70] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-02-27 5:41 ` [PATCH 10/70] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2023-03-06 15:15 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 11/70] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-06 15:22 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 12/70] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
2023-03-06 13:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 13/70] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:49 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 14/70] target/cris: " Richard Henderson
2023-03-07 0:30 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 15/70] target/hexagon: Use tcg_constant_* for gen_constant_from_imm Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 17/70] target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 18/70] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 19/70] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 22:00 ` Richard Henderson
2023-02-27 22:38 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
2023-03-06 13:50 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 22/70] target/i386: Simplify POPF Richard Henderson
2023-02-27 9:04 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
2023-03-07 0:37 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 24/70] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
2023-02-27 5:41 ` [PATCH 25/70] target/m68k: Use tcg_constant_i32 " Richard Henderson
2023-03-06 14:14 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
2023-03-06 23:53 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
2023-03-07 0:03 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 23:59 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 29/70] target/microblaze: " Richard Henderson
2023-02-27 8:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 30/70] target/mips: Split out gen_lxl Richard Henderson
2023-03-06 13:31 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 31/70] target/mips: Split out gen_lxr Richard Henderson
2023-03-06 13:40 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
2023-03-06 13:41 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 33/70] target/mips: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 13:46 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 34/70] target/ppc: Split out gen_vx_vmul10 Richard Henderson
2023-03-06 15:08 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
2023-03-06 14:16 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 36/70] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-02-27 5:42 ` [PATCH 37/70] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 38/70] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-02-27 5:42 ` [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 40/70] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 41/70] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 42/70] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-02-27 5:42 ` [PATCH 43/70] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-02-27 5:42 ` [PATCH 44/70] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-02-27 5:42 ` [PATCH 45/70] target/riscv: Avoid tcg_const_* Richard Henderson
2023-02-27 9:05 ` Philippe Mathieu-Daudé
2023-03-06 13:53 ` liweiwei
2023-02-27 5:42 ` [PATCH 46/70] target/rx: Use tcg_gen_abs_i32 Richard Henderson
2023-03-06 13:48 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
2023-03-07 0:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
2023-03-06 14:18 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 49/70] target/rx: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:27 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 50/70] target/s390x: Split out gen_ri2 Richard Henderson
2023-02-27 9:09 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 51/70] target/s390x: Avoid tcg_const_i64 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 52/70] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
2023-03-07 0:23 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 53/70] target/sh4: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 54/70] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
2023-03-06 15:36 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32} Richard Henderson
2023-03-01 17:02 ` Mark Cave-Ayland
2023-03-06 15:37 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable Richard Henderson
2023-03-07 0:19 ` Philippe Mathieu-Daudé
2023-03-07 2:24 ` Richard Henderson
2023-03-07 10:20 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 57/70] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
2023-03-06 15:38 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 58/70] target/tricore: Use min/max for saturate Richard Henderson
2023-02-27 5:53 ` Richard Henderson
2023-02-27 5:42 ` [PATCH 59/70] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
2023-03-06 15:39 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 60/70] target/tricore: Drop some temp initialization Richard Henderson
2023-03-06 15:25 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 61/70] target/tricore: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:10 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 62/70] target/xtensa: Tidy translate_bb Richard Henderson
2023-02-27 9:19 ` Max Filippov
2023-03-07 0:07 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 63/70] target/xtensa: Tidy translate_clamps Richard Henderson
2023-02-27 9:22 ` Max Filippov
2023-03-07 0:24 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r Richard Henderson
2023-02-27 9:23 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll Richard Henderson
2023-02-27 9:26 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 66/70] target/xtensa: Split constant in bit shift Richard Henderson
2023-02-27 9:27 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 67/70] target/xtensa: Avoid tcg_const_i32 Richard Henderson
2023-02-27 9:31 ` Max Filippov
2023-03-07 0:06 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 68/70] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
2023-03-06 15:33 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 69/70] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-06 15:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 70/70] tcg: Drop tcg_const_* Richard Henderson
2023-03-06 15:30 ` Philippe Mathieu-Daudé
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