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From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Huacai Chen" <chenhuacai@kernel.org>,
	"Gerd Hoffmann" <kraxel@redhat.com>,
	qemu-ppc@nongnu.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"BALATON Zoltan" <balaton@eik.bme.hu>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v3 2/3] hw/isa/vt82c686: Implement PCI IRQ routing
Date: Mon, 27 Feb 2023 13:33:15 +0100	[thread overview]
Message-ID: <20230227123316.18719-3-shentey@gmail.com> (raw)
In-Reply-To: <20230227123316.18719-1-shentey@gmail.com>

The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
 hw/isa/vt82c686.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 3f9bd0c04d..7aea97365f 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -604,6 +604,45 @@ static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
     qemu_set_irq(s->cpu_intr, level);
 }
 
+static unsigned via_isa_get_pci_irq(const ViaISAState *s, int irq_num)
+{
+    switch (irq_num) {
+    case 0:
+        return s->dev.config[0x55] >> 4;
+
+    case 1:
+        return s->dev.config[0x56] & 0xf;
+
+    case 2:
+        return s->dev.config[0x56] >> 4;
+
+    case 3:
+        return s->dev.config[0x57] >> 4;
+    }
+
+    return 0;
+}
+
+static void via_isa_set_pci_irq(void *opaque, int irq_num, int level)
+{
+    ViaISAState *s = opaque;
+    PCIBus *bus = pci_get_bus(&s->dev);
+    unsigned pic_irq = via_isa_get_pci_irq(s, irq_num);
+    int i, pic_level = 0;
+
+    assert(pic_irq < ISA_NUM_IRQS);
+
+    /* The PIC level is the logical OR of all the PCI irqs mapped to it. */
+    for (i = 0; i < PCI_NUM_PINS; i++) {
+        if (pic_irq == via_isa_get_pci_irq(s, i)) {
+            pic_level |= pci_bus_get_irq_level(bus, i);
+        }
+    }
+
+    /* Now we change the pic irq level according to the via irq mappings. */
+    qemu_set_irq(s->isa_irqs[pic_irq], pic_level);
+}
+
 static void via_isa_realize(PCIDevice *d, Error **errp)
 {
     ViaISAState *s = VIA_ISA(d);
@@ -676,6 +715,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
     if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) {
         return;
     }
+
+    pci_bus_irqs(pci_bus, via_isa_set_pci_irq, s, PCI_NUM_PINS);
 }
 
 /* TYPE_VT82C686B_ISA */
-- 
2.39.2



  parent reply	other threads:[~2023-02-27 12:34 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-27 12:33 [PATCH v3 0/3] VT82xx PCI IRQ routing fixes Bernhard Beschow
2023-02-27 12:33 ` [PATCH v3 1/3] hw/ppc/pegasos2: Initialize VT8231 PCI IRQ router Bernhard Beschow
2023-02-27 12:33 ` Bernhard Beschow [this message]
2023-02-27 12:33 ` [PATCH v3 3/3] hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing Bernhard Beschow
2023-02-27 12:40 ` [PATCH v3 0/3] VT82xx PCI IRQ routing fixes BALATON Zoltan

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