From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"John Snow" <jsnow@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Weiwei Li" <liweiwei@iscas.ac.cn>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
qemu-arm@nongnu.org, qemu-riscv@nongnu.org
Subject: [PULL 006/123] target/cpu: Restrict do_transaction_failed() handlers to sysemu
Date: Mon, 27 Feb 2023 13:36:50 +0100 [thread overview]
Message-ID: <20230227123847.27110-7-philmd@linaro.org> (raw)
In-Reply-To: <20230227123847.27110-1-philmd@linaro.org>
The 'hwaddr' type is only available / meaningful on system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216215519.5522-6-philmd@linaro.org>
---
target/arm/internals.h | 2 ++
target/m68k/cpu.h | 2 ++
target/riscv/cpu.h | 10 +++++-----
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 759b70c646..2ad4fc4633 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -614,6 +614,7 @@ G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
+#ifndef CONFIG_USER_ONLY
/* arm_cpu_do_transaction_failed: handle a memory system error response
* (eg "no device/memory present at address") by raising an external abort
* exception
@@ -623,6 +624,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+#endif
/* Call any registered EL change hooks */
static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 68ed531fc3..048d5aae2b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -581,10 +581,12 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#ifndef CONFIG_USER_ONLY
void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+#endif
#include "exec/cpu-all.h"
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index df9cbc0d3f..d8e72c3e7c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -579,11 +579,6 @@ G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
@@ -591,6 +586,11 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
--
2.38.1
next prev parent reply other threads:[~2023-02-27 12:42 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 12:36 [PULL 000/123] Buildsys / QOM / QDev / UI patches for 2023-02-27 Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 001/123] cpu: Remove capstone meson dependency Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 002/123] cpu: Move breakpoint helpers to common code Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 003/123] cputlb: Restrict SavedIOTLB to system emulation Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 004/123] gdbstub: Use vaddr type for generic insert/remove_breakpoint() API Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 005/123] target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu Philippe Mathieu-Daudé
2023-02-27 12:36 ` Philippe Mathieu-Daudé [this message]
2023-02-27 12:36 ` [PULL 007/123] target/i386: Remove NEED_CPU_H guard from target-specific headers Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 008/123] target/i386/cpu: Remove dead helper_lock() declaration Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 009/123] target/i386: Remove x86_cpu_dump_local_apic_state() dead stub Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 010/123] target/hppa: Extract FPU helpers to fpu_helper.c Philippe Mathieu-Daudé
2023-02-27 12:36 ` [PULL 011/123] target/hppa: Extract system helpers to sys_helper.c Philippe Mathieu-Daudé
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