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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>
Subject: [PULL 04/62] accel/tcg: Add 'size' param to probe_access_full
Date: Tue, 28 Feb 2023 16:55:45 -1000	[thread overview]
Message-ID: <20230301025643.1227244-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230301025643.1227244-1-richard.henderson@linaro.org>

Change to match the recent change to probe_access_flags.
All existing callers updated to supply 0, so no change in behaviour.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/exec-all.h              | 2 +-
 accel/tcg/cputlb.c                   | 4 ++--
 target/arm/ptw.c                     | 2 +-
 target/arm/tcg/mte_helper.c          | 4 ++--
 target/arm/tcg/sve_helper.c          | 2 +-
 target/arm/tcg/translate-a64.c       | 2 +-
 target/i386/tcg/sysemu/excp_helper.c | 4 ++--
 7 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 165b050872..b631832e17 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -475,7 +475,7 @@ int probe_access_flags(CPUArchState *env, target_ulong addr, int size,
  * and must be consumed or copied immediately, before any further
  * access or changes to TLB @mmu_idx.
  */
-int probe_access_full(CPUArchState *env, target_ulong addr,
+int probe_access_full(CPUArchState *env, target_ulong addr, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool nonfault, void **phost,
                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index fc27e34457..008ae7a66d 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1589,12 +1589,12 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     return flags;
 }
 
-int probe_access_full(CPUArchState *env, target_ulong addr,
+int probe_access_full(CPUArchState *env, target_ulong addr, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool nonfault, void **phost, CPUTLBEntryFull **pfull,
                       uintptr_t retaddr)
 {
-    int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
+    int flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
                                       nonfault, phost, pfull, retaddr);
 
     /* Handle clean RAM pages.  */
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index cf3f2fd703..8541ef56d6 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -259,7 +259,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
         int flags;
 
         env->tlb_fi = fi;
-        flags = probe_access_full(env, addr, MMU_DATA_LOAD,
+        flags = probe_access_full(env, addr, 0, MMU_DATA_LOAD,
                                   arm_to_core_mmu_idx(s2_mmu_idx),
                                   true, &ptw->out_host, &full, 0);
         env->tlb_fi = NULL;
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index 98bcf59c22..fee3c7eb96 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -118,7 +118,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      * valid.  Indicate to probe_access_flags no-fault, then assert that
      * we received a valid page.
      */
-    flags = probe_access_full(env, ptr, ptr_access, ptr_mmu_idx,
+    flags = probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx,
                               ra == 0, &host, &full, ra);
     assert(!(flags & TLB_INVALID_MASK));
 
@@ -154,7 +154,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      */
     in_page = -(ptr | TARGET_PAGE_MASK);
     if (unlikely(ptr_size > in_page)) {
-        flags |= probe_access_full(env, ptr + in_page, ptr_access,
+        flags |= probe_access_full(env, ptr + in_page, 0, ptr_access,
                                    ptr_mmu_idx, ra == 0, &host, &full, ra);
         assert(!(flags & TLB_INVALID_MASK));
     }
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index 51909c44ac..9a8951afa4 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -5356,7 +5356,7 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
                                &info->host, retaddr);
 #else
     CPUTLBEntryFull *full;
-    flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
+    flags = probe_access_full(env, addr, 0, access_type, mmu_idx, nofault,
                               &info->host, &full, retaddr);
 #endif
     info->flags = flags;
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index da9f877476..67e9c4ee79 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -14651,7 +14651,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
      * that the TLB entry must be present and valid, and thus this
      * access will never raise an exception.
      */
-    flags = probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx,
+    flags = probe_access_full(env, addr, 0, MMU_INST_FETCH, mmu_idx,
                               false, &host, &full, 0);
     assert(!(flags & TLB_INVALID_MASK));
 
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index 55bd1194d3..e87f90dbe3 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -64,7 +64,7 @@ static bool ptw_translate(PTETranslate *inout, hwaddr addr)
     int flags;
 
     inout->gaddr = addr;
-    flags = probe_access_full(inout->env, addr, MMU_DATA_STORE,
+    flags = probe_access_full(inout->env, addr, 0, MMU_DATA_STORE,
                               inout->ptw_idx, true, &inout->haddr, &full, 0);
 
     if (unlikely(flags & TLB_INVALID_MASK)) {
@@ -428,7 +428,7 @@ do_check_protect_pse36:
         CPUTLBEntryFull *full;
         int flags, nested_page_size;
 
-        flags = probe_access_full(env, paddr, access_type,
+        flags = probe_access_full(env, paddr, 0, access_type,
                                   MMU_NESTED_IDX, true,
                                   &pte_trans.haddr, &full, 0);
         if (unlikely(flags & TLB_INVALID_MASK)) {
-- 
2.34.1



  parent reply	other threads:[~2023-03-01  2:57 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-01  2:55 [PULL 00/62] tcg patch queue Richard Henderson
2023-03-01  2:55 ` [PULL 01/62] exec/helper-head: Include missing "fpu/softfloat-types.h" header Richard Henderson
2023-03-01  2:55 ` [PULL 02/62] softmmu: Use memmove in flatview_write_continue Richard Henderson
2023-03-01  2:55 ` [PULL 03/62] accel/tcg: Add 'size' param to probe_access_flags() Richard Henderson
2023-03-01  2:55 ` Richard Henderson [this message]
2023-03-01  2:55 ` [PULL 05/62] include/exec: Introduce `CF_PCREL` Richard Henderson
2023-03-01  2:55 ` [PULL 06/62] target/i386: set `CF_PCREL` in `x86_cpu_realizefn` Richard Henderson
2023-03-01  2:55 ` [PULL 07/62] target/arm: set `CF_PCREL` in `arm_cpu_realizefn` Richard Henderson
2023-03-01  2:55 ` [PULL 08/62] accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL` Richard Henderson
2023-03-01  2:55 ` [PULL 09/62] include/exec: " Richard Henderson
2023-03-01  2:55 ` [PULL 10/62] target/arm: " Richard Henderson
2023-03-01  2:55 ` [PULL 11/62] target/i386: " Richard Henderson
2023-03-01  2:55 ` [PULL 12/62] include/exec: Remove `TARGET_TB_PCREL` define Richard Henderson
2023-03-01  2:55 ` [PULL 13/62] target/arm: " Richard Henderson
2023-03-01  2:55 ` [PULL 14/62] target/i386: " Richard Henderson
2023-03-01  2:55 ` [PULL 15/62] accel/tcg: Move jmp-cache `CF_PCREL` checks to caller Richard Henderson
2023-03-01  2:55 ` [PULL 16/62] accel/tcg: Replace `tb_pc()` with `tb->pc` Richard Henderson
2023-03-01  2:55 ` [PULL 17/62] target/tricore: " Richard Henderson
2023-03-01  2:55 ` [PULL 18/62] target/sparc: " Richard Henderson
2023-03-01  2:56 ` [PULL 19/62] target/sh4: " Richard Henderson
2023-03-01  2:56 ` [PULL 20/62] target/rx: " Richard Henderson
2023-03-01  2:56 ` [PULL 21/62] target/riscv: " Richard Henderson
2023-03-01  2:56 ` [PULL 22/62] target/openrisc: " Richard Henderson
2023-03-01  2:56 ` [PULL 23/62] target/mips: " Richard Henderson
2023-03-01  2:56 ` [PULL 24/62] target/microblaze: " Richard Henderson
2023-03-01  2:56 ` [PULL 25/62] target/loongarch: " Richard Henderson
2023-03-01  2:56 ` [PULL 26/62] target/i386: " Richard Henderson
2023-03-01  2:56 ` [PULL 27/62] target/hppa: " Richard Henderson
2023-03-01  2:56 ` [PULL 28/62] target/hexagon: " Richard Henderson
2023-03-01  2:56 ` [PULL 29/62] target/avr: " Richard Henderson
2023-03-01  2:56 ` [PULL 30/62] target/arm: " Richard Henderson
2023-03-01  2:56 ` [PULL 31/62] include/exec: Remove `tb_pc()` Richard Henderson
2023-03-01  2:56 ` [PULL 32/62] tcg: Adjust TCGContext.temps_in_use check Richard Henderson
2023-03-01  2:56 ` [PULL 33/62] accel/tcg: Pass max_insn to gen_intermediate_code by pointer Richard Henderson
2023-03-01  2:56 ` [PULL 34/62] accel/tcg: Use more accurate max_insns for tb_overflow Richard Henderson
2023-03-01  2:56 ` [PULL 35/62] tcg: Remove branch-to-next regardless of reference count Richard Henderson
2023-03-01  2:56 ` [PULL 36/62] tcg: Rename TEMP_LOCAL to TEMP_TB Richard Henderson
2023-03-01  2:56 ` [PULL 37/62] tcg: Use noinline for major tcg_gen_code subroutines Richard Henderson
2023-03-01  2:56 ` [PULL 38/62] tcg: Add liveness_pass_0 Richard Henderson
2023-03-01  2:56 ` [PULL 39/62] tcg: Remove TEMP_NORMAL Richard Henderson
2023-03-01  2:56 ` [PULL 40/62] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
2023-03-01  2:56 ` [PULL 41/62] tcg: Use tcg_constant_i32 in tcg_gen_io_start Richard Henderson
2023-03-01  2:56 ` [PULL 42/62] tcg: Add tcg_gen_movi_ptr Richard Henderson
2023-03-01  2:56 ` [PULL 43/62] tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} Richard Henderson
2023-03-01  2:56 ` [PULL 44/62] tcg: Use tcg_temp_ebb_new_* in tcg/ Richard Henderson
2023-03-01  2:56 ` [PULL 45/62] tcg: Use tcg_constant_ptr in do_dup Richard Henderson
2023-03-01  2:56 ` [PULL 46/62] accel/tcg/plugin: Use tcg_temp_ebb_* Richard Henderson
2023-03-01  2:56 ` [PULL 47/62] accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers Richard Henderson
2023-03-01  2:56 ` [PULL 48/62] tcg: Don't re-use TEMP_TB temporaries Richard Henderson
2023-03-01  2:56 ` [PULL 49/62] tcg: Change default temp lifetime to TEMP_TB Richard Henderson
2023-03-01  2:56 ` [PULL 50/62] target/arm: Drop copies in gen_sve_{ldr,str} Richard Henderson
2023-03-01  2:56 ` [PULL 51/62] target/arm: Don't use tcg_temp_local_new_* Richard Henderson
2023-03-01  2:56 ` [PULL 52/62] target/cris: Don't use tcg_temp_local_new Richard Henderson
2023-03-01  2:56 ` [PULL 53/62] target/hexagon: Don't use tcg_temp_local_new_* Richard Henderson
2023-03-01  2:56 ` [PULL 54/62] target/hexagon/idef-parser: Drop gen_tmp_local Richard Henderson
2023-03-01  2:56 ` [PULL 55/62] target/hppa: Don't use tcg_temp_local_new Richard Henderson
2023-03-01  2:56 ` [PULL 56/62] target/i386: " Richard Henderson
2023-03-01  2:56 ` [PULL 57/62] target/mips: " Richard Henderson
2023-03-01  2:56 ` [PULL 58/62] target/ppc: " Richard Henderson
2023-03-01  2:56 ` [PULL 59/62] target/xtensa: Don't use tcg_temp_local_new_* Richard Henderson
2023-03-01  2:56 ` [PULL 60/62] exec/gen-icount: Don't use tcg_temp_local_new_i32 Richard Henderson
2023-03-01  2:56 ` [PULL 61/62] tcg: Remove tcg_temp_local_new_*, tcg_const_local_* Richard Henderson
2023-03-01  2:56 ` [PULL 62/62] tcg: Update docs/devel/tcg-ops.rst for temporary changes Richard Henderson
2023-03-01 11:07 ` [PULL 00/62] tcg patch queue Peter Maydell

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