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From: Tao Su <tao1.su@linux.intel.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, richard.henderson@linaro.org,
	yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com,
	philmd@linaro.org
Subject: [PATCH v2 5/6] target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration
Date: Fri,  3 Mar 2023 14:59:12 +0800	[thread overview]
Message-ID: <20230303065913.1246327-6-tao1.su@linux.intel.com> (raw)
In-Reply-To: <20230303065913.1246327-1-tao1.su@linux.intel.com>

From: Jiaxi Chen <jiaxi.chen@linux.intel.com>

AVX-NE-CONVERT is a new set of instructions which can convert low
precision floating point like BF16/FP16 to high precision floating point
FP32, as well as convert FP32 elements to BF16. This instruction allows
the platform to have improved AI capabilities and better compatibility.

The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 5]

Add CPUID definition for AVX-NE-CONVERT.

Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 246d10aa49..eee1e5c25f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -892,7 +892,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
             NULL, NULL, NULL, NULL,
-            "avx-vnni-int8", NULL, NULL, NULL,
+            "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d53b960f23..14876938c1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -920,6 +920,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 
 /* Support for VPDPB[SU,UU,SS]D[,S] */
 #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
+/* AVX NE CONVERT Instructions */
+#define CPUID_7_1_EDX_AVX_NE_CONVERT    (1U << 5)
 
 /* XFD Extend Feature Disabled */
 #define CPUID_D_1_EAX_XFD               (1U << 4)
-- 
2.34.1



  parent reply	other threads:[~2023-03-03  7:01 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03  6:59 [PATCH v2 0/6] target/i386: Support new Intel platform Instructions in CPUID enumeration Tao Su
2023-03-03  6:59 ` [PATCH v2 1/6] target/i386: Add support for CMPCCXADD " Tao Su
2023-03-03  6:59 ` [PATCH v2 2/6] target/i386: Add support for AMX-FP16 " Tao Su
2023-03-03  6:59 ` [PATCH v2 3/6] target/i386: Add support for AVX-IFMA " Tao Su
2023-03-03  6:59 ` [PATCH v2 4/6] target/i386: Add support for AVX-VNNI-INT8 " Tao Su
2023-03-03  6:59 ` Tao Su [this message]
2023-03-03  6:59 ` [PATCH v2 6/6] target/i386: Add support for PREFETCHIT0/1 " Tao Su
2023-03-04  4:04 ` [PATCH v2 0/6] target/i386: Support new Intel platform Instructions " Xiaoyao Li
2023-04-26 12:24 ` Paolo Bonzini
2023-04-27  1:39   ` Tao Su

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