From: Palmer Dabbelt <palmer@rivosinc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Weiwei Li <liweiwei@iscas.ac.cn>, Bin Meng <bmeng@tinylab.org>,
Andrew Jones <ajones@ventanamicro.com>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa()
Date: Fri, 3 Mar 2023 00:36:43 -0800 [thread overview]
Message-ID: <20230303083740.12817-3-palmer@rivosinc.com> (raw)
In-Reply-To: <20230303083740.12817-1-palmer@rivosinc.com>
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.
If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230222185205.355361-3-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/csr.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1b0a0c1693..e149b453da 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
/* Mask extensions that are not supported by this hart */
val &= env->misa_ext_mask;
- /* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
-
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
val &= ~RVD;
--
2.39.2
next prev parent reply other threads:[~2023-03-03 8:50 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-03 8:36 [PULL 00/59] Fifth RISC-V PR for QEMU 8.0 Palmer Dabbelt
2023-03-03 8:36 ` [PULL 01/59] target/riscv: introduce riscv_cpu_cfg() Palmer Dabbelt
2023-03-03 8:36 ` Palmer Dabbelt [this message]
2023-03-03 8:36 ` [PULL 03/59] target/riscv: allow MISA writes as experimental Palmer Dabbelt
2023-03-03 8:36 ` [PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG Palmer Dabbelt
2023-03-03 8:36 ` [PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP Palmer Dabbelt
2023-03-03 8:36 ` [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP Palmer Dabbelt
2023-03-03 8:36 ` [PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP Palmer Dabbelt
2023-03-03 8:36 ` [PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() Palmer Dabbelt
2023-03-03 8:36 ` [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU Palmer Dabbelt
2023-03-03 8:36 ` [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends Palmer Dabbelt
2023-03-03 8:36 ` [PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh Palmer Dabbelt
2023-03-03 8:36 ` [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx Palmer Dabbelt
2023-03-03 8:36 ` [PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin Palmer Dabbelt
2023-03-03 8:36 ` [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions Palmer Dabbelt
2023-03-03 8:36 ` [PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D Palmer Dabbelt
2023-03-03 8:36 ` [PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions Palmer Dabbelt
2023-03-03 8:36 ` [PULL 17/59] target/riscv: Indent fixes in cpu.c Palmer Dabbelt
2023-03-03 8:36 ` [PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f Palmer Dabbelt
2023-03-03 8:37 ` [PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc Palmer Dabbelt
2023-03-03 8:37 ` [PULL 20/59] target/riscv: Remove redundunt check for zve32f and zve64f Palmer Dabbelt
2023-03-03 8:37 ` [PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions Palmer Dabbelt
2023-03-03 8:37 ` [PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64 Palmer Dabbelt
2023-03-03 8:37 ` [PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc Palmer Dabbelt
2023-03-03 8:37 ` [PULL 24/59] target/riscv: Expose properties for Zv* extensions Palmer Dabbelt
2023-03-03 8:37 ` [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR Palmer Dabbelt
2023-03-03 8:37 ` [PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check Palmer Dabbelt
2023-03-03 8:37 ` [PULL 28/59] target/riscv: gdbstub: Minor change for better readability Palmer Dabbelt
2023-03-03 8:37 ` [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Palmer Dabbelt
2023-03-03 8:37 ` [PULL 30/59] target/riscv: Coding style fixes in csr.c Palmer Dabbelt
2023-03-03 8:37 ` [PULL 31/59] target/riscv: Use 'bool' type for read_only Palmer Dabbelt
2023-03-03 8:37 ` [PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit Palmer Dabbelt
2023-03-03 8:37 ` [PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env Palmer Dabbelt
2023-03-03 8:37 ` [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Palmer Dabbelt
2023-03-03 8:37 ` [PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Palmer Dabbelt
2023-03-03 8:37 ` [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs Palmer Dabbelt
2023-03-03 8:37 ` [PULL 38/59] target/riscv: Allow debugger to access seed CSR Palmer Dabbelt
2023-03-03 8:37 ` [PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs Palmer Dabbelt
2023-03-03 8:37 ` [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs Palmer Dabbelt
2023-03-03 8:37 ` [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 42/59] target/riscv: Group all predicate() routines together Palmer Dabbelt
2023-03-03 8:37 ` [PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages Palmer Dabbelt
2023-03-03 8:37 ` [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair Palmer Dabbelt
2023-03-03 8:37 ` [PULL 45/59] target/riscv: Add support for Zicond extension Palmer Dabbelt
2023-03-03 8:37 ` [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB Palmer Dabbelt
2023-03-03 8:37 ` [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Palmer Dabbelt
2023-03-03 8:37 ` [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Palmer Dabbelt
2023-03-03 8:37 ` [PULL 50/59] target/riscv: Add csr support for svadu Palmer Dabbelt
2023-03-03 8:37 ` [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation Palmer Dabbelt
2023-03-03 8:37 ` [PULL 52/59] target/riscv: Add *envcfg.HADE " Palmer Dabbelt
2023-03-03 8:37 ` [PULL 53/59] target/riscv: Export Svadu property Palmer Dabbelt
2023-03-03 8:37 ` [PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 55/59] target/riscv/csr.c: simplify mctr() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers Palmer Dabbelt
2023-03-03 8:37 ` [PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig Palmer Dabbelt
2023-03-03 8:37 ` [PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s() Palmer Dabbelt
2023-03-03 8:37 ` [PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig Palmer Dabbelt
2023-03-03 12:20 ` [PULL 00/59] Fifth RISC-V PR for QEMU 8.0 Peter Maydell
2023-03-03 13:35 ` Peter Maydell
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