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[77.183.4.175]) by smtp.gmail.com with ESMTPSA id h7-20020a170906398700b008dd6bf721c2sm2170540eje.106.2023.03.04.07.27.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 07:27:05 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH v2 10/13] hw/pci-host/q35: Rename local variable to more idiomatic "phb" Date: Sat, 4 Mar 2023 16:26:45 +0100 Message-Id: <20230304152648.103749-11-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304152648.103749-1-shentey@gmail.com> References: <20230304152648.103749-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Variables of type PCIHostState* are typically named "phb" in QEMU. Follow this convention here as well for consistency. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index afd192cc2a..cf9fb35064 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -46,21 +46,21 @@ static void q35_host_realize(DeviceState *dev, Error **errp) { - PCIHostState *pci = PCI_HOST_BRIDGE(dev); Q35PCIHost *s = Q35_HOST_DEVICE(dev); + PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); memory_region_add_subregion(s->mch.address_space_io, - MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); + MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); memory_region_add_subregion(s->mch.address_space_io, - MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); + MCH_HOST_BRIDGE_CONFIG_DATA, &phb->data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); /* register q35 0xcf8 port as coalesced pio */ - memory_region_set_flush_coalesced(&pci->data_mem); - memory_region_add_coalescing(&pci->conf_mem, 0, 4); + memory_region_set_flush_coalesced(&phb->data_mem); + memory_region_add_coalescing(&phb->conf_mem, 0, 4); /* * pci hole goes from end-of-low-ram to io-apic. @@ -69,12 +69,12 @@ static void q35_host_realize(DeviceState *dev, Error **errp) range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); - pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", + phb->bus = pci_root_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); - qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); + qdev_realize(DEVICE(&s->mch), BUS(phb->bus), &error_fatal); } static const char *q35_host_root_bus_path(PCIHostState *host_bridge, -- 2.39.2