From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: Eduardo Habkost <eduardo@habkost.net>,
"Michael S. Tsirkin" <mst@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Bernhard Beschow <shentey@gmail.com>
Subject: [PATCH v2 12/13] hw/pci-host/q35: Merge mch_realize() into q35_host_realize()
Date: Sat, 4 Mar 2023 16:26:47 +0100 [thread overview]
Message-ID: <20230304152648.103749-13-shentey@gmail.com> (raw)
In-Reply-To: <20230304152648.103749-1-shentey@gmail.com>
This patch prepares movement of the MemoryRegion pointers (which are set
through properties) into the host state. Moreover, it's usually the
parent device which maps the memory regions of its child devices into
its address space. Do the same in q35.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/pci-host/q35.c | 209 ++++++++++++++++++++++------------------------
1 file changed, 101 insertions(+), 108 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 39d70b9f59..1e0f5b4fbf 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -44,12 +44,40 @@
#define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35)
+static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size)
+{
+ return 0xffffffff;
+}
+
+static void blackhole_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ /* nothing */
+}
+
+static const MemoryRegionOps blackhole_ops = {
+ .read = blackhole_read,
+ .write = blackhole_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+};
+
static void q35_host_realize(DeviceState *dev, Error **errp)
{
ERRP_GUARD();
Q35PCIHost *s = Q35_HOST_DEVICE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ int i;
+
+ if (s->mch.ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) {
+ error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16,
+ s->mch.ext_tseg_mbytes);
+ return;
+ }
memory_region_add_subregion(s->mch.address_space_io,
MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_mem);
@@ -70,6 +98,79 @@ static void q35_host_realize(DeviceState *dev, Error **errp)
range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size,
IO_APIC_DEFAULT_ADDRESS - 1);
+ /* setup pci memory mapping */
+ pc_pci_as_mapping_init(s->mch.system_memory, s->mch.pci_address_space);
+
+ /* if *disabled* show SMRAM to all CPUs */
+ memory_region_init_alias(&s->mch.smram_region, OBJECT(s), "smram-region",
+ s->mch.pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ MCH_HOST_BRIDGE_SMRAM_C_SIZE);
+ memory_region_add_subregion_overlap(s->mch.system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ &s->mch.smram_region, 1);
+ memory_region_set_enabled(&s->mch.smram_region, true);
+
+ memory_region_init_alias(&s->mch.open_high_smram, OBJECT(s), "smram-open-high",
+ s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ MCH_HOST_BRIDGE_SMRAM_C_SIZE);
+ memory_region_add_subregion_overlap(s->mch.system_memory, 0xfeda0000,
+ &s->mch.open_high_smram, 1);
+ memory_region_set_enabled(&s->mch.open_high_smram, false);
+
+ /* smram, as seen by SMM CPUs */
+ memory_region_init_alias(&s->mch.low_smram, OBJECT(s), "smram-low",
+ s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ MCH_HOST_BRIDGE_SMRAM_C_SIZE);
+ memory_region_set_enabled(&s->mch.low_smram, true);
+ memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ &s->mch.low_smram);
+ memory_region_init_alias(&s->mch.high_smram, OBJECT(s), "smram-high",
+ s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ MCH_HOST_BRIDGE_SMRAM_C_SIZE);
+ memory_region_set_enabled(&s->mch.high_smram, true);
+ memory_region_add_subregion(s->mch.smram, 0xfeda0000, &s->mch.high_smram);
+
+ memory_region_init_io(&s->mch.tseg_blackhole, OBJECT(s),
+ &blackhole_ops, NULL, "tseg-blackhole", 0);
+ memory_region_set_enabled(&s->mch.tseg_blackhole, false);
+ memory_region_add_subregion_overlap(s->mch.system_memory,
+ s->mch.below_4g_mem_size,
+ &s->mch.tseg_blackhole, 1);
+
+ memory_region_init_alias(&s->mch.tseg_window, OBJECT(s), "tseg-window",
+ s->mch.ram_memory, s->mch.below_4g_mem_size, 0);
+ memory_region_set_enabled(&s->mch.tseg_window, false);
+ memory_region_add_subregion(s->mch.smram, s->mch.below_4g_mem_size,
+ &s->mch.tseg_window);
+
+ /*
+ * This is not what hardware does, so it's QEMU specific hack.
+ * See commit message for details.
+ */
+ memory_region_init_io(&s->mch.smbase_blackhole, OBJECT(s), &blackhole_ops,
+ NULL, "smbase-blackhole",
+ MCH_HOST_BRIDGE_SMBASE_SIZE);
+ memory_region_set_enabled(&s->mch.smbase_blackhole, false);
+ memory_region_add_subregion_overlap(s->mch.system_memory,
+ MCH_HOST_BRIDGE_SMBASE_ADDR,
+ &s->mch.smbase_blackhole, 1);
+
+ memory_region_init_alias(&s->mch.smbase_window, OBJECT(s),
+ "smbase-window", s->mch.ram_memory,
+ MCH_HOST_BRIDGE_SMBASE_ADDR,
+ MCH_HOST_BRIDGE_SMBASE_SIZE);
+ memory_region_set_enabled(&s->mch.smbase_window, false);
+ memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMBASE_ADDR,
+ &s->mch.smbase_window);
+
+ init_pam(&s->mch.pam_regions[0], OBJECT(s), s->mch.ram_memory,
+ s->mch.system_memory, s->mch.pci_address_space,
+ PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ for (i = 0; i < ARRAY_SIZE(s->mch.pam_regions) - 1; ++i) {
+ init_pam(&s->mch.pam_regions[i + 1], OBJECT(s), s->mch.ram_memory,
+ s->mch.system_memory, s->mch.pci_address_space,
+ PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
+ }
+
phb->bus = pci_root_bus_new(DEVICE(s), "pcie.0",
s->mch.pci_address_space,
s->mch.address_space_io,
@@ -277,27 +378,6 @@ static const TypeInfo q35_host_info = {
* MCH D0:F0
*/
-static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size)
-{
- return 0xffffffff;
-}
-
-static void blackhole_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned width)
-{
- /* nothing */
-}
-
-static const MemoryRegionOps blackhole_ops = {
- .read = blackhole_read,
- .write = blackhole_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
- .impl.min_access_size = 4,
- .impl.max_access_size = 4,
-};
-
/* PCIe MMCFG */
static void mch_update_pciexbar(MCHPCIState *mch)
{
@@ -560,92 +640,6 @@ static void mch_reset(DeviceState *qdev)
mch_update(mch);
}
-static void mch_realize(PCIDevice *d, Error **errp)
-{
- int i;
- MCHPCIState *mch = MCH_PCI_DEVICE(d);
-
- if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) {
- error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16,
- mch->ext_tseg_mbytes);
- return;
- }
-
- /* setup pci memory mapping */
- pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space);
-
- /* if *disabled* show SMRAM to all CPUs */
- memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
- mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE,
- MCH_HOST_BRIDGE_SMRAM_C_SIZE);
- memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
- &mch->smram_region, 1);
- memory_region_set_enabled(&mch->smram_region, true);
-
- memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
- mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
- MCH_HOST_BRIDGE_SMRAM_C_SIZE);
- memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
- &mch->open_high_smram, 1);
- memory_region_set_enabled(&mch->open_high_smram, false);
-
- /* smram, as seen by SMM CPUs */
- memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
- mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
- MCH_HOST_BRIDGE_SMRAM_C_SIZE);
- memory_region_set_enabled(&mch->low_smram, true);
- memory_region_add_subregion(mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE,
- &mch->low_smram);
- memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
- mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
- MCH_HOST_BRIDGE_SMRAM_C_SIZE);
- memory_region_set_enabled(&mch->high_smram, true);
- memory_region_add_subregion(mch->smram, 0xfeda0000, &mch->high_smram);
-
- memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
- &blackhole_ops, NULL,
- "tseg-blackhole", 0);
- memory_region_set_enabled(&mch->tseg_blackhole, false);
- memory_region_add_subregion_overlap(mch->system_memory,
- mch->below_4g_mem_size,
- &mch->tseg_blackhole, 1);
-
- memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
- mch->ram_memory, mch->below_4g_mem_size, 0);
- memory_region_set_enabled(&mch->tseg_window, false);
- memory_region_add_subregion(mch->smram, mch->below_4g_mem_size,
- &mch->tseg_window);
-
- /*
- * This is not what hardware does, so it's QEMU specific hack.
- * See commit message for details.
- */
- memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops,
- NULL, "smbase-blackhole",
- MCH_HOST_BRIDGE_SMBASE_SIZE);
- memory_region_set_enabled(&mch->smbase_blackhole, false);
- memory_region_add_subregion_overlap(mch->system_memory,
- MCH_HOST_BRIDGE_SMBASE_ADDR,
- &mch->smbase_blackhole, 1);
-
- memory_region_init_alias(&mch->smbase_window, OBJECT(mch),
- "smbase-window", mch->ram_memory,
- MCH_HOST_BRIDGE_SMBASE_ADDR,
- MCH_HOST_BRIDGE_SMBASE_SIZE);
- memory_region_set_enabled(&mch->smbase_window, false);
- memory_region_add_subregion(mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR,
- &mch->smbase_window);
-
- init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory,
- mch->system_memory, mch->pci_address_space,
- PAM_BIOS_BASE, PAM_BIOS_SIZE);
- for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) {
- init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory,
- mch->system_memory, mch->pci_address_space,
- PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
- }
-}
-
uint64_t mch_mcfg_base(void)
{
bool ambiguous;
@@ -668,7 +662,6 @@ static void mch_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- k->realize = mch_realize;
k->config_write = mch_write_config;
dc->reset = mch_reset;
device_class_set_props(dc, mch_props);
--
2.39.2
next prev parent reply other threads:[~2023-03-04 15:28 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-04 15:26 [PATCH v2 00/13] Q35 PCI host fixes and QOM cleanup Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 01/13] hw/i386/pc_q35: Resolve redundant q35_host variable Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 02/13] hw/pci-host/q35: Fix double, contradicting .endianness assignment Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 03/13] hw/pci-host/q35: Use memory_region_set_address() also for tseg_blackhole Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 04/13] hw/pci-host/q35: Initialize PCMachineState::bus in board code Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 05/13] hw/pci/pci_host: Introduce PCI_HOST_BYPASS_IOMMU macro Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 06/13] hw/pci-host/q35: Initialize "bypass-iommu" property from board code Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 07/13] hw/pci-host/q35: Initialize properties just once Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 08/13] hw/pci-host/q35: Initialize PCI hole boundaries " Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 09/13] hw/pci-host/q35: Turn PCI hole properties into class properties Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 10/13] hw/pci-host/q35: Rename local variable to more idiomatic "phb" Bernhard Beschow
2023-03-04 15:26 ` [PATCH v2 11/13] hw/pci-host/q35: Propagate to errp rather than doing error_fatal Bernhard Beschow
2023-03-04 15:26 ` Bernhard Beschow [this message]
2023-03-04 15:26 ` [PATCH v2 13/13] hw/pci-host/q35: Move MemoryRegion pointers to host device Bernhard Beschow
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