From: Palmer Dabbelt <palmer@rivosinc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Mayuresh Chitale <mchitale@ventanamicro.com>,
Anup Patel <apatel@ventanamicro.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PULL 06/22] target/riscv: cpu: Implement get_arch_id callback
Date: Mon, 6 Mar 2023 14:02:43 -0800 [thread overview]
Message-ID: <20230306220259.7748-7-palmer@rivosinc.com> (raw)
In-Reply-To: <20230306220259.7748-1-palmer@rivosinc.com>
From: Mayuresh Chitale <mchitale@ventanamicro.com>
Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230303065055.915652-2-mchitale@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3e8f21a47d..0ad8f94a42 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1301,6 +1301,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
}
#ifndef CONFIG_USER_ONLY
+static int64_t riscv_get_arch_id(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ return cpu->env.mhartid;
+}
+
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps riscv_sysemu_ops = {
@@ -1355,6 +1362,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &riscv_sysemu_ops;
+ cc->get_arch_id = riscv_get_arch_id;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
--
2.39.2
next prev parent reply other threads:[~2023-03-06 22:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-06 22:02 [PULL 00/22] Sixth RISC-V PR for 8.0 Palmer Dabbelt
2023-03-06 22:02 ` [PULL 01/22] target/riscv: implement Zicboz extension Palmer Dabbelt
2023-03-06 22:02 ` [PULL 02/22] target/riscv: implement Zicbom extension Palmer Dabbelt
2023-03-06 22:02 ` [PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder Palmer Dabbelt
2023-03-06 22:02 ` [PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties Palmer Dabbelt
2023-03-06 22:02 ` [PULL 05/22] disas/riscv Fix ctzw disassemble Palmer Dabbelt
2023-03-06 22:02 ` Palmer Dabbelt [this message]
2023-03-06 22:02 ` [PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state Palmer Dabbelt
2023-03-06 22:02 ` [PULL 08/22] gitlab/opensbi: Move to docker:stable Palmer Dabbelt
2023-03-06 22:02 ` [PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2 Palmer Dabbelt
2023-03-06 22:02 ` [PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState Palmer Dabbelt
2023-03-06 22:02 ` [PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool Palmer Dabbelt
2023-03-06 22:02 ` [PULL 12/22] riscv: Allow user to set the satp mode Palmer Dabbelt
2023-03-06 22:02 ` [PULL 13/22] riscv: Introduce satp mode hw capabilities Palmer Dabbelt
2023-03-06 22:02 ` [PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type' Palmer Dabbelt
2023-03-06 22:02 ` [PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields Palmer Dabbelt
2023-03-06 22:02 ` [PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI Palmer Dabbelt
2023-03-06 22:02 ` [PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState Palmer Dabbelt
2023-03-06 22:02 ` [PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure Palmer Dabbelt
2023-03-06 22:02 ` [PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT Palmer Dabbelt
2023-03-06 22:02 ` [PULL 20/22] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table Palmer Dabbelt
2023-03-06 22:02 ` [PULL 21/22] hw/riscv/virt.c: Initialize the ACPI tables Palmer Dabbelt
2023-03-06 22:02 ` [PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI Palmer Dabbelt
2023-03-07 14:33 ` [PULL 00/22] Sixth RISC-V PR for 8.0 Peter Maydell
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