From: Palmer Dabbelt <palmer@rivosinc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Mayuresh Chitale <mchitale@ventanamicro.com>,
Anup Patel <apatel@ventanamicro.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state
Date: Mon, 6 Mar 2023 14:02:44 -0800 [thread overview]
Message-ID: <20230306220259.7748-8-palmer@rivosinc.com> (raw)
In-Reply-To: <20230306220259.7748-1-palmer@rivosinc.com>
From: Mayuresh Chitale <mchitale@ventanamicro.com>
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the
CPU state. However APLIC, IMSIC and ACLINT contain registers and states
which are specific to physical hart Ids. The hart Ids in any given system
might be sparse and hence calls to qemu_get_cpu need to be replaced by
cpu_by_arch_id which performs lookup based on the sparse physical hart IDs.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230303065055.915652-3-mchitale@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
hw/intc/riscv_aclint.c | 16 ++++++++--------
hw/intc/riscv_aplic.c | 4 ++--
hw/intc/riscv_imsic.c | 6 +++---
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index eee04643cb..b466a6abaf 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -130,7 +130,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -173,7 +173,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -231,7 +231,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
/* Check if timer interrupt is triggered for each hart. */
for (i = 0; i < mtimer->num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
continue;
@@ -292,7 +292,7 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
s->timecmp = g_new0(uint64_t, s->num_harts);
/* Claim timer interrupt bits */
for (i = 0; i < s->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
+ RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
error_report("MTIP already claimed");
exit(1);
@@ -372,7 +372,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
riscv_aclint_mtimer_callback *cb =
@@ -407,7 +407,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -430,7 +430,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -545,7 +545,7 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
qdev_connect_gpio_out(dev, i,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index cfd007e629..cd7efc4ad4 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -833,7 +833,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
/* Claim the CPU interrupt to be triggered by this APLIC */
for (i = 0; i < aplic->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(aplic->hartid_base + i));
+ RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu,
(aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
error_report("%s already claimed",
@@ -966,7 +966,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
if (!msimode) {
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
qdev_connect_gpio_out_named(dev, NULL, i,
qdev_get_gpio_in(DEVICE(cpu),
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index 4d4d5b50ca..fea3385b51 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -316,8 +316,8 @@ static const MemoryRegionOps riscv_imsic_ops = {
static void riscv_imsic_realize(DeviceState *dev, Error **errp)
{
RISCVIMSICState *imsic = RISCV_IMSIC(dev);
- RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
- CPUState *cpu = qemu_get_cpu(imsic->hartid);
+ RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid));
+ CPUState *cpu = cpu_by_arch_id(imsic->hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
@@ -413,7 +413,7 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
uint32_t num_pages, uint32_t num_ids)
{
DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
uint32_t i;
assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
--
2.39.2
next prev parent reply other threads:[~2023-03-06 22:07 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-06 22:02 [PULL 00/22] Sixth RISC-V PR for 8.0 Palmer Dabbelt
2023-03-06 22:02 ` [PULL 01/22] target/riscv: implement Zicboz extension Palmer Dabbelt
2023-03-06 22:02 ` [PULL 02/22] target/riscv: implement Zicbom extension Palmer Dabbelt
2023-03-06 22:02 ` [PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder Palmer Dabbelt
2023-03-06 22:02 ` [PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties Palmer Dabbelt
2023-03-06 22:02 ` [PULL 05/22] disas/riscv Fix ctzw disassemble Palmer Dabbelt
2023-03-06 22:02 ` [PULL 06/22] target/riscv: cpu: Implement get_arch_id callback Palmer Dabbelt
2023-03-06 22:02 ` Palmer Dabbelt [this message]
2023-03-06 22:02 ` [PULL 08/22] gitlab/opensbi: Move to docker:stable Palmer Dabbelt
2023-03-06 22:02 ` [PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2 Palmer Dabbelt
2023-03-06 22:02 ` [PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState Palmer Dabbelt
2023-03-06 22:02 ` [PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool Palmer Dabbelt
2023-03-06 22:02 ` [PULL 12/22] riscv: Allow user to set the satp mode Palmer Dabbelt
2023-03-06 22:02 ` [PULL 13/22] riscv: Introduce satp mode hw capabilities Palmer Dabbelt
2023-03-06 22:02 ` [PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type' Palmer Dabbelt
2023-03-06 22:02 ` [PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields Palmer Dabbelt
2023-03-06 22:02 ` [PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI Palmer Dabbelt
2023-03-06 22:02 ` [PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState Palmer Dabbelt
2023-03-06 22:02 ` [PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure Palmer Dabbelt
2023-03-06 22:02 ` [PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT Palmer Dabbelt
2023-03-06 22:02 ` [PULL 20/22] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table Palmer Dabbelt
2023-03-06 22:02 ` [PULL 21/22] hw/riscv/virt.c: Initialize the ACPI tables Palmer Dabbelt
2023-03-06 22:02 ` [PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI Palmer Dabbelt
2023-03-07 14:33 ` [PULL 00/22] Sixth RISC-V PR for 8.0 Peter Maydell
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