From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, "BALATON Zoltan" <balaton@eik.bme.hu>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Rene Engel" <ReneEngel80@emailn.de>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing
Date: Wed, 8 Mar 2023 00:47:05 +0100 [thread overview]
Message-ID: <20230307234711.55375-15-philmd@linaro.org> (raw)
In-Reply-To: <20230307234711.55375-1-philmd@linaro.org>
From: BALATON Zoltan <balaton@eik.bme.hu>
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get interrupts from
either of these. So far we only had the MV64361 connections which
worked for on board devices but for additional PCI devices (such as
network or sound card added with -device) guest OSes expect interrupt
from the ISA IRQ 9 where the firmware routes these PCI interrupts in
VT8231 ISA bridge. After the previous patches we can now model this
and also remove the board specific connection from mv64361. Also
configure routing of these lines when using Virtual Open Firmware to
match board firmware for guests that expect this.
This fixes PCI interrupts on pegasos2 under Linux, MorphOS and AmigaOS.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Message-Id: <520ff9e6eeef600ee14a4116c0c7b11940cc499c.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/pci-host/mv64361.c | 4 ----
hw/ppc/pegasos2.c | 26 +++++++++++++++++++++++++-
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
index 298564f1f5..19e8031a3f 100644
--- a/hw/pci-host/mv64361.c
+++ b/hw/pci-host/mv64361.c
@@ -873,10 +873,6 @@ static void mv64361_realize(DeviceState *dev, Error **errp)
}
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq);
qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32);
- /* FIXME: PCI IRQ connections may be board specific */
- for (i = 0; i < PCI_NUM_PINS; i++) {
- s->pci[1].irq[i] = qdev_get_gpio_in_named(dev, "gpp", 12 + i);
- }
}
static void mv64361_reset(DeviceState *dev)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 7cc375df05..f1650be5ee 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -73,6 +73,8 @@ struct Pegasos2MachineState {
MachineState parent_obj;
PowerPCCPU *cpu;
DeviceState *mv;
+ qemu_irq mv_pirq[PCI_NUM_PINS];
+ qemu_irq via_pirq[PCI_NUM_PINS];
Vof *vof;
void *fdt_blob;
uint64_t kernel_addr;
@@ -95,6 +97,15 @@ static void pegasos2_cpu_reset(void *opaque)
}
}
+static void pegasos2_pci_irq(void *opaque, int n, int level)
+{
+ Pegasos2MachineState *pm = opaque;
+
+ /* PCI interrupt lines are connected to both MV64361 and VT8231 */
+ qemu_set_irq(pm->mv_pirq[n], level);
+ qemu_set_irq(pm->via_pirq[n], level);
+}
+
static void pegasos2_init(MachineState *machine)
{
Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
@@ -106,7 +117,7 @@ static void pegasos2_init(MachineState *machine)
I2CBus *i2c_bus;
const char *fwname = machine->firmware ?: PROM_FILENAME;
char *filename;
- int sz;
+ int i, sz;
uint8_t *spd_data;
/* init CPU */
@@ -156,11 +167,18 @@ static void pegasos2_init(MachineState *machine)
/* Marvell Discovery II system controller */
pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i);
+ }
pci_bus = mv64361_get_pci_bus(pm->mv, 1);
+ pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS);
/* VIA VT8231 South Bridge (multifunction PCI device) */
via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0),
true, TYPE_VT8231_ISA));
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i);
+ }
object_property_add_alias(OBJECT(machine), "rtc-time",
object_resolve_path_component(via, "rtc"),
"date");
@@ -267,6 +285,12 @@ static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason)
PCI_INTERRUPT_LINE, 2, 0x9);
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
0x50, 1, 0x2);
+ pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
+ 0x55, 1, 0x90);
+ pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
+ 0x56, 1, 0x99);
+ pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
+ 0x57, 1, 0x90);
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
PCI_INTERRUPT_LINE, 2, 0x109);
--
2.38.1
next prev parent reply other threads:[~2023-03-07 23:48 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-07 23:46 [PULL 00/20] MIPS patches for 2023-03-07 Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 01/20] docs/system: Remove "mips" board from target-mips.rst Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 02/20] target/mips: Replace [g_]assert(0) -> g_assert_not_reached() Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microMIPS Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 04/20] target/mips: Fix SWM32 " Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 05/20] target/mips: Implement CP0.Config7.WII bit support Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 06/20] target/mips: Set correct CP0.Config[4, 5] values for M14K(c) Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 07/20] hw/mips: Declare all length properties as unsigned Philippe Mathieu-Daudé
2023-03-07 23:46 ` [PULL 08/20] hw/mips/itu: Pass SAAR using QOM link property Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 09/20] Revert "hw/isa/i82378: Remove intermediate IRQ forwarder" Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 10/20] Revert "hw/isa/vt82c686: " Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 11/20] hw/display/sm501: Add debug property to control pixman usage Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 12/20] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 13/20] hw/isa/vt82c686: Implement PCI IRQ routing Philippe Mathieu-Daudé
2023-03-07 23:47 ` Philippe Mathieu-Daudé [this message]
2023-03-08 13:54 ` [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing Philippe Mathieu-Daudé
2023-03-08 14:46 ` BALATON Zoltan
2023-03-08 18:51 ` BALATON Zoltan
2023-03-07 23:47 ` [PULL 15/20] hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 16/20] hw/audio/via-ac97: Basic implementation of audio playback Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 17/20] hw/usb/ohci: Implement resume on connection status change Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 18/20] ui/cocoa: Override windowDidResignKey Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 19/20] memory: Dump HPA and access type of ramblocks Philippe Mathieu-Daudé
2023-03-07 23:47 ` [PULL 20/20] log: Remove unneeded new line Philippe Mathieu-Daudé
2023-03-09 13:13 ` [PULL 00/20] MIPS patches for 2023-03-07 Peter Maydell
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