From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
Date: Thu, 9 Mar 2023 15:13:27 +0800 [thread overview]
Message-ID: <20230309071329.45932-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230309071329.45932-1-liweiwei@iscas.ac.cn>
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index b8e56d2b7b..a200741083 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
return true;
}
- cpu = RISCV_CPU(env_cpu(env));
+ cpu = env_archcpu(env);
if (!cpu->pmu_event_ctr_map) {
return false;
}
@@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
return true;
}
- cpu = RISCV_CPU(env_cpu(env));
+ cpu = env_archcpu(env);
if (!cpu->pmu_event_ctr_map) {
return false;
}
@@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx)
{
uint32_t event_idx;
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ RISCVCPU *cpu = env_archcpu(env);
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
return -1;
@@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
{
uint64_t overflow_delta, overflow_at;
int64_t overflow_ns, overflow_left = 0;
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ RISCVCPU *cpu = env_archcpu(env);
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
--
2.25.1
next prev parent reply other threads:[~2023-03-09 7:14 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 7:13 [PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification Weiwei Li
2023-03-09 7:13 ` [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Weiwei Li
2023-03-09 20:52 ` Daniel Henrique Barboza
2023-03-14 5:23 ` Alistair Francis
2023-03-09 7:13 ` Weiwei Li [this message]
2023-03-09 20:54 ` [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env Daniel Henrique Barboza
2023-03-14 5:24 ` Alistair Francis
2023-03-14 5:52 ` Philippe Mathieu-Daudé
2023-03-09 7:13 ` [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState Weiwei Li
2023-03-09 20:56 ` Daniel Henrique Barboza
2023-03-14 5:29 ` Alistair Francis
2023-03-09 7:13 ` [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check Weiwei Li
2023-03-09 20:57 ` Daniel Henrique Barboza
2023-03-14 5:30 ` Alistair Francis
2023-03-14 5:54 ` Philippe Mathieu-Daudé
2023-03-15 4:57 ` [PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification Alistair Francis
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