From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v2 40/91] target/avr: Avoid use of tcg_const_i32 throughout
Date: Thu, 9 Mar 2023 12:04:59 -0800 [thread overview]
Message-ID: <20230309200550.3878088-41-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230309200550.3878088-1-richard.henderson@linaro.org>
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/translate.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 190d0c3f97..a6aeae6dfa 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -400,7 +400,7 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a)
static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv Rr = tcg_const_i32(a->imm);
+ TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */
@@ -425,7 +425,7 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -453,9 +453,9 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv Rr = tcg_const_i32(a->imm);
+ TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -637,7 +637,7 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a)
static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv t0 = tcg_const_i32(0);
+ TCGv t0 = tcg_constant_i32(0);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
@@ -930,19 +930,19 @@ static void gen_jmp_z(DisasContext *ctx)
static void gen_push_ret(DisasContext *ctx, int ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
- TCGv t0 = tcg_const_i32((ret & 0x0000ff));
+ TCGv t0 = tcg_constant_i32(ret & 0x0000ff);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
- TCGv t0 = tcg_const_i32((ret & 0x00ffff));
+ TCGv t0 = tcg_constant_i32(ret & 0x00ffff);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
- TCGv lo = tcg_const_i32((ret & 0x0000ff));
- TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
+ TCGv lo = tcg_constant_i32(ret & 0x0000ff);
+ TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8);
tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
@@ -1211,7 +1211,7 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -1238,7 +1238,7 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
{
TCGv Rd = cpu_r[a->rd];
int Imm = a->imm;
- TCGv Rr = tcg_const_i32(Imm);
+ TCGv Rr = tcg_constant_i32(Imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
@@ -2124,7 +2124,7 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
static bool trans_IN(DisasContext *ctx, arg_IN *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv port = tcg_const_i32(a->imm);
+ TCGv port = tcg_constant_i32(a->imm);
gen_helper_inb(Rd, cpu_env, port);
return true;
@@ -2137,7 +2137,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv port = tcg_const_i32(a->imm);
+ TCGv port = tcg_constant_i32(a->imm);
gen_helper_outb(cpu_env, port, Rd);
return true;
@@ -2405,7 +2405,7 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
{
TCGv data = tcg_temp_new_i32();
- TCGv port = tcg_const_i32(a->reg);
+ TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
@@ -2420,7 +2420,7 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
{
TCGv data = tcg_temp_new_i32();
- TCGv port = tcg_const_i32(a->reg);
+ TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
--
2.34.1
next prev parent reply other threads:[~2023-03-09 20:11 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
2023-03-09 20:04 ` [PULL v2 01/91] target/mips: Drop tcg_temp_free from micromips_translate.c.inc Richard Henderson
2023-03-09 20:04 ` [PULL v2 02/91] target/mips: Drop tcg_temp_free from msa_translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 03/91] target/mips: Drop tcg_temp_free from mxu_translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 04/91] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc Richard Henderson
2023-03-09 20:04 ` [PULL v2 05/91] target/mips: Drop tcg_temp_free from octeon_translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 06/91] target/mips: Drop tcg_temp_free from translate_addr_const.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 07/91] target/mips: Drop tcg_temp_free from tx79_translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 08/91] target/mips: Drop tcg_temp_free from vr54xx_translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 09/91] target/mips: Drop tcg_temp_free from translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 10/91] target/s390x: Drop free_compare Richard Henderson
2023-03-09 20:04 ` [PULL v2 11/91] target/s390x: Drop tcg_temp_free from translate_vx.c.inc Richard Henderson
2023-03-09 20:04 ` [PULL v2 12/91] target/s390x: Drop tcg_temp_free from translate.c Richard Henderson
2023-03-09 20:04 ` [PULL v2 13/91] target/s390x: Remove assert vs g_in2 Richard Henderson
2023-03-09 20:04 ` [PULL v2 14/91] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext Richard Henderson
2023-03-09 20:04 ` [PULL v2 15/91] tcg: Create tcg/tcg-temp-internal.h Richard Henderson
2023-03-09 20:04 ` [PULL v2 16/91] include/exec: Set default `NB_MMU_MODES` to 16 Richard Henderson
2023-03-09 20:04 ` [PULL v2 17/91] target/alpha: Remove `NB_MMU_MODES` define Richard Henderson
2023-03-09 20:04 ` [PULL v2 18/91] target/arm: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 19/91] target/avr: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 20/91] target/cris: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 21/91] target/hexagon: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 22/91] target/hppa: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 23/91] target/i386: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 24/91] target/loongarch: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 25/91] target/m68k: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 26/91] target/microblaze: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 27/91] target/mips: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 28/91] target/nios2: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 29/91] target/openrisc: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 30/91] target/ppc: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 31/91] target/riscv: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 32/91] target/rx: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 33/91] target/s390x: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 34/91] target/sh4: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 35/91] target/sparc: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 36/91] target/tricore: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 37/91] target/xtensa: " Richard Henderson
2023-03-09 20:04 ` [PULL v2 38/91] include/exec: Remove guards around `NB_MMU_MODES` Richard Henderson
2023-03-09 20:04 ` [PULL v2 39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
2023-03-09 20:04 ` Richard Henderson [this message]
2023-03-09 20:05 ` [PULL v2 41/91] target/cris: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-09 20:05 ` [PULL v2 42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
2023-03-09 20:05 ` [PULL v2 43/91] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-09 20:05 ` [PULL v2 44/91] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
2023-03-09 20:05 ` [PULL v2 45/91] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
2023-03-09 20:05 ` [PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
2023-03-09 20:05 ` [PULL v2 47/91] target/m68k: Avoid tcg_const_* throughout Richard Henderson
2023-03-09 20:05 ` [PULL v2 48/91] target/mips: Split out gen_lxl Richard Henderson
2023-03-09 20:05 ` [PULL v2 49/91] target/mips: Split out gen_lxr Richard Henderson
2023-03-09 20:05 ` [PULL v2 50/91] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
2023-03-09 20:05 ` [PULL v2 51/91] target/mips: Avoid tcg_const_* throughout Richard Henderson
2023-03-09 20:05 ` [PULL v2 52/91] target/ppc: Split out gen_vx_vmul10 Richard Henderson
2023-03-09 20:05 ` [PULL v2 53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
2023-03-09 20:05 ` [PULL v2 54/91] target/rx: Use tcg_gen_abs_i32 Richard Henderson
2023-03-09 20:05 ` [PULL v2 55/91] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
2023-03-09 20:05 ` [PULL v2 56/91] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
2023-03-09 20:05 ` [PULL v2 57/91] target/rx: Avoid tcg_const_i32 Richard Henderson
2023-03-09 20:05 ` [PULL v2 58/91] target/s390x: Avoid tcg_const_i64 Richard Henderson
2023-03-09 20:05 ` [PULL v2 59/91] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
2023-03-09 20:05 ` [PULL v2 60/91] target/sh4: Avoid tcg_const_i32 Richard Henderson
2023-03-09 20:05 ` [PULL v2 61/91] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
2023-03-09 20:05 ` [PULL v2 62/91] target/tricore: Split t_n as constant from temp as variable Richard Henderson
2023-03-09 20:05 ` [PULL v2 63/91] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
2023-03-09 20:05 ` [PULL v2 64/91] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
2023-03-09 20:05 ` [PULL v2 65/91] target/tricore: Drop some temp initialization Richard Henderson
2023-03-09 20:05 ` [PULL v2 66/91] target/tricore: Avoid tcg_const_i32 Richard Henderson
2023-03-09 20:05 ` [PULL v2 67/91] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
2023-03-09 20:05 ` [PULL v2 68/91] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-09 20:05 ` [PULL v2 69/91] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-03-09 20:05 ` [PULL v2 70/91] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-09 20:05 ` [PULL v2 71/91] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-09 20:05 ` [PULL v2 72/91] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
2023-03-09 20:05 ` [PULL v2 73/91] target/arm: Improve trans_BFCI Richard Henderson
2023-03-09 20:05 ` [PULL v2 74/91] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
2023-03-09 20:05 ` [PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-03-09 20:05 ` [PULL v2 76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-03-09 20:05 ` [PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2024-01-23 15:09 ` Peter Maydell
2023-03-09 20:05 ` [PULL v2 78/91] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-09 20:05 ` [PULL v2 79/91] target/m68k: Use tcg_constant_i32 in gen_ea_mode Richard Henderson
2023-03-09 20:05 ` [PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-03-09 20:05 ` [PULL v2 81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-03-09 20:05 ` [PULL v2 82/91] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-03-09 20:05 ` [PULL v2 83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-03-09 20:05 ` [PULL v2 84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-03-09 20:05 ` [PULL v2 85/91] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-03-09 20:05 ` [PULL v2 86/91] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-03-09 20:05 ` [PULL v2 87/91] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-03-09 20:05 ` [PULL v2 88/91] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-03-09 20:05 ` [PULL v2 89/91] target/tricore: Use min/max for saturate Richard Henderson
2023-03-09 20:05 ` [PULL v2 90/91] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-09 20:05 ` [PULL v2 91/91] tcg: Drop tcg_const_* Richard Henderson
2023-03-11 17:16 ` [PULL v2 00/91] tcg patch queue Peter Maydell
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