* [PULL v2 01/91] target/mips: Drop tcg_temp_free from micromips_translate.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 02/91] target/mips: Drop tcg_temp_free from msa_translate.c Richard Henderson
` (90 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/micromips_translate.c.inc | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 632895cc9e..23f80d4315 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -724,9 +724,6 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
break;
#endif
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free_i32(t2);
}
@@ -1018,8 +1015,6 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
break;
#endif
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
@@ -1067,7 +1062,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_load_gpr(t0, rt);
gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
- tcg_temp_free(t0);
}
break;
#endif
@@ -1276,7 +1270,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
* mode.
*/
ctx->base.is_jmp = DISAS_STOP;
- tcg_temp_free(t0);
}
break;
case EI:
@@ -1293,7 +1286,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
*/
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- tcg_temp_free(t0);
}
break;
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 02/91] target/mips: Drop tcg_temp_free from msa_translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
2023-03-09 20:04 ` [PULL v2 01/91] target/mips: Drop tcg_temp_free from micromips_translate.c.inc Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 03/91] target/mips: Drop tcg_temp_free from mxu_translate.c Richard Henderson
` (89 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/msa_translate.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1bcdbb1121..220cd3b048 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -217,8 +217,6 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
/* if some bit is non-zero then some element is zero */
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(tresult, t0);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
}
static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
@@ -237,7 +235,6 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(bcond, t0);
- tcg_temp_free_i64(t0);
ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
@@ -545,8 +542,6 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
gen_load_gpr(telm, a->ws);
gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));
- tcg_temp_free(telm);
-
return true;
}
@@ -563,8 +558,6 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd);
- tcg_temp_free(telm);
-
return true;
}
@@ -782,8 +775,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr);
- tcg_temp_free(taddr);
-
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 03/91] target/mips: Drop tcg_temp_free from mxu_translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
2023-03-09 20:04 ` [PULL v2 01/91] target/mips: Drop tcg_temp_free from micromips_translate.c.inc Richard Henderson
2023-03-09 20:04 ` [PULL v2 02/91] target/mips: Drop tcg_temp_free from msa_translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 04/91] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc Richard Henderson
` (88 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/mxu_translate.c | 51 ---------------------------------
1 file changed, 51 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index f52244e1b2..8703b0cef4 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -513,8 +513,6 @@ static void gen_mxu_s32i2m(DisasContext *ctx)
} else if (XRa == 16) {
gen_store_mxu_cr(t0);
}
-
- tcg_temp_free(t0);
}
/*
@@ -537,8 +535,6 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
}
gen_store_gpr(t0, Rb);
-
- tcg_temp_free(t0);
}
/*
@@ -613,9 +609,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
}
gen_store_mxu_gpr(t0, XRa);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/*
@@ -664,11 +657,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
}
gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
- tcg_temp_free(t3);
}
/*
@@ -741,11 +729,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
}
gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
- tcg_temp_free(t3);
}
/*
@@ -821,15 +804,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
gen_store_mxu_gpr(t0, XRd);
gen_store_mxu_gpr(t1, XRa);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
- tcg_temp_free(t3);
- tcg_temp_free(t4);
- tcg_temp_free(t5);
- tcg_temp_free(t6);
- tcg_temp_free(t7);
}
/*
@@ -860,9 +834,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
gen_store_mxu_gpr(t1, XRa);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
@@ -1125,9 +1096,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
tcg_gen_shri_i32(t0, t0, 16);
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
} else if (unlikely(XRb == XRc)) {
/* both operands same -> just set destination to one of them */
tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
@@ -1161,9 +1129,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
tcg_gen_shri_i32(t0, t0, 16);
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
}
}
@@ -1226,9 +1191,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
} else if (unlikely(XRb == XRc)) {
/* both operands same -> just set destination to one of them */
tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
@@ -1266,9 +1228,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
}
}
@@ -1384,9 +1343,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 24);
tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN2:
@@ -1410,9 +1366,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 16);
tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN3:
@@ -1436,9 +1389,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 8);
tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN4:
@@ -1598,7 +1548,6 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
}
gen_set_label(l_exit);
- tcg_temp_free(t_mxu_cr);
}
return true;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 04/91] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 03/91] target/mips: Drop tcg_temp_free from mxu_translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 05/91] target/mips: Drop tcg_temp_free from octeon_translate.c Richard Henderson
` (87 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/nanomips_translate.c.inc | 127 ++---------------------
1 file changed, 10 insertions(+), 117 deletions(-)
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index faf6d679bd..b3df7fec40 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1005,13 +1005,9 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
}
gen_store_gpr(tmp1, reg1);
- tcg_temp_free(tmp1);
gen_store_gpr(tmp2, reg2);
- tcg_temp_free(tmp2);
tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
- tcg_temp_free_i64(tval);
tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
- tcg_temp_free(taddr);
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
@@ -1084,9 +1080,6 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
/* adjust stack pointer */
gen_adjust_sp(ctx, -u);
-
- tcg_temp_free(t0);
- tcg_temp_free(va);
}
static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
@@ -1110,9 +1103,6 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
/* adjust stack pointer */
gen_adjust_sp(ctx, u);
-
- tcg_temp_free(t0);
- tcg_temp_free(va);
}
static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
@@ -1232,8 +1222,6 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
if (insn_bytes == 2) {
ctx->hflags |= MIPS_HFLAG_B16;
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
@@ -1358,7 +1346,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
- tcg_temp_free(t0);
#endif
} else {
gen_slt(ctx, OPC_SLTU, rd, rs, rt);
@@ -1381,10 +1368,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
/* operands of same sign, result different sign */
tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0);
gen_store_gpr(t0, rd);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
}
break;
case NM_MUL:
@@ -1427,7 +1410,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3));
- tcg_temp_free(t0);
}
break;
case NM_D_E_MT_VPE:
@@ -1467,8 +1449,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
-
- tcg_temp_free(t0);
}
break;
case NM_FORK:
@@ -1480,8 +1460,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
gen_helper_fork(t0, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
break;
case NM_MFTR:
@@ -1508,7 +1486,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rs);
gen_helper_yield(t0, cpu_env, t0);
gen_store_gpr(t0, rt);
- tcg_temp_free(t0);
}
break;
#endif
@@ -1557,11 +1534,6 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
-
- tcg_temp_free_i32(t0);
-
- tcg_temp_free(v0_t);
- tcg_temp_free(v1_t);
}
@@ -1682,10 +1654,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(v0_t);
}
static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
@@ -1802,8 +1770,6 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
-
- tcg_temp_free_i32(t0);
}
static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
@@ -1855,10 +1821,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case NM_MULT:
@@ -1878,8 +1842,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_muls2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case NM_EXTRV_W:
@@ -1915,10 +1877,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case NM_MULTU:
@@ -1938,8 +1898,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mulu2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case NM_EXTRV_R_W:
@@ -1982,10 +1940,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case NM_EXTRV_RS_W:
@@ -2027,10 +1983,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case NM_EXTRV_S_H:
@@ -2045,12 +1999,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-
- tcg_temp_free(v0_t);
- tcg_temp_free(v1_t);
}
static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
@@ -2162,7 +2110,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_load_gpr(tv0, rt);
gen_helper_insv(v0_t, cpu_env, v0_t, tv0);
gen_store_gpr(v0_t, ret);
- tcg_temp_free(tv0);
}
break;
case NM_RADDU_W_QB:
@@ -2188,9 +2135,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
-
- tcg_temp_free(v0_t);
- tcg_temp_free(t0);
}
static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
@@ -2243,8 +2187,6 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
- tcg_temp_free(t0);
- tcg_temp_free(rs_t);
}
@@ -2304,7 +2246,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- tcg_temp_free(t0);
}
break;
case NM_EI:
@@ -2317,7 +2258,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- tcg_temp_free(t0);
}
break;
case NM_RDPGPR:
@@ -2374,7 +2314,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
/* Unconditional branch */
} else if (rt == 0 && imm != 0) {
/* Treat as NOP */
- goto out;
+ return;
} else {
cond = TCG_COND_EQ;
}
@@ -2384,12 +2324,12 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
check_nms(ctx);
if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
gen_reserved_instruction(ctx);
- goto out;
+ return;
} else if (rt == 0 && opc == NM_BBEQZC) {
/* Unconditional branch */
} else if (rt == 0 && opc == NM_BBNEZC) {
/* Treat as NOP */
- goto out;
+ return;
} else {
tcg_gen_shri_tl(t0, t0, imm);
tcg_gen_andi_tl(t0, t0, 1);
@@ -2404,7 +2344,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
case NM_BNEIC:
if (rt == 0 && imm == 0) {
/* Treat as NOP */
- goto out;
+ return;
} else if (rt == 0 && imm != 0) {
/* Unconditional branch */
} else {
@@ -2434,7 +2374,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Immediate Value Compact branch");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
/* branch completion */
@@ -2455,10 +2395,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
}
-
-out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
@@ -2488,9 +2424,6 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
/* unconditional branch to register */
tcg_gen_mov_tl(cpu_PC, btarget);
tcg_gen_lookup_and_goto_ptr();
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* nanoMIPS Branches */
@@ -2540,14 +2473,12 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
gen_load_gpr(tbase, rt);
tcg_gen_movi_tl(toffset, offset);
gen_op_addr_add(ctx, btarget, tbase, toffset);
- tcg_temp_free(tbase);
- tcg_temp_free(toffset);
}
break;
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
if (bcond_compute == 0) {
@@ -2559,7 +2490,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
} else {
/* Conditional compact branch */
@@ -2620,7 +2551,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Compact conditional branch/jump");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
/* branch completion */
@@ -2633,10 +2564,6 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
}
-
-out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
@@ -2664,15 +2591,12 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
default:
MIPS_INVAL("cp1 cond branch");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
tcg_gen_trunc_i64_tl(bcond, t0);
ctx->btarget = btarget;
-
-out:
- tcg_temp_free_i64(t0);
}
@@ -2709,7 +2633,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
break;
default:
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
@@ -2799,10 +2723,6 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
gen_reserved_instruction(ctx);
break;
}
-
-out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
@@ -3443,7 +3363,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
- tcg_temp_free_i32(sa_t);
}
break;
case 1:
@@ -3453,7 +3372,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
- tcg_temp_free_i32(sa_t);
}
break;
}
@@ -3536,8 +3454,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
tcg_gen_movi_tl(tv0, rd >> 3);
tcg_gen_movi_tl(tv1, imm);
gen_helper_shilo(tv0, tv1, cpu_env);
- tcg_temp_free(tv1);
- tcg_temp_free(tv0);
}
break;
case NM_MULEQ_S_W_PHL:
@@ -3652,10 +3568,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_reserved_instruction(ctx);
break;
}
-
- tcg_temp_free(v2_t);
- tcg_temp_free(v1_t);
- tcg_temp_free(t0);
}
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
@@ -3827,7 +3739,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
- tcg_temp_free(t0);
}
break;
case NM_SWPC48:
@@ -3844,9 +3755,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
break;
default:
@@ -3908,8 +3816,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rs);
tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm);
gen_store_gpr(t0, rt);
-
- tcg_temp_free(t0);
}
break;
case NM_ADDIUNEG:
@@ -3965,11 +3871,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rs);
gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
- tcg_temp_free(t0);
-
- tcg_temp_free_i32(shift);
- tcg_temp_free_i32(shiftx);
- tcg_temp_free_i32(stripe);
}
break;
case NM_P_INS:
@@ -4239,8 +4140,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
MO_UNALN);
break;
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
break;
case NM_P_LL:
@@ -4432,8 +4331,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
counter++;
}
- tcg_temp_free(va);
- tcg_temp_free(t1);
}
break;
default:
@@ -4454,7 +4351,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
- tcg_temp_free(t0);
}
break;
case NM_P_BAL:
@@ -4606,7 +4502,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
if (ctx->base.pc_next & 0x1) {
TCGv tmp = tcg_const_tl(ctx->base.pc_next);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
- tcg_temp_free(tmp);
generate_exception_end(ctx, EXCP_AdEL);
return 2;
}
@@ -4941,8 +4836,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
tcg_gen_mov_tl(cpu_gpr[re], t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
break;
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 05/91] target/mips: Drop tcg_temp_free from octeon_translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 04/91] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 06/91] target/mips: Drop tcg_temp_free from translate_addr_const.c Richard Henderson
` (86 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/octeon_translate.c | 23 -----------------------
1 file changed, 23 deletions(-)
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index 6a207d2e7e..103c304d10 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -40,8 +40,6 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
ctx->hflags |= MIPS_HFLAG_BC;
ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
ctx->hflags |= MIPS_HFLAG_BDS32;
-
- tcg_temp_free(t0);
return true;
}
@@ -61,10 +59,6 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-
return true;
}
@@ -83,10 +77,6 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
gen_load_gpr(t1, a->rt);
tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-
return true;
}
@@ -103,8 +93,6 @@ static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
gen_load_gpr(t0, a->rs);
tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
- tcg_temp_free(t0);
-
return true;
}
@@ -121,8 +109,6 @@ static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
gen_load_gpr(t0, a->rs);
tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
- tcg_temp_free(t0);
-
return true;
}
@@ -142,8 +128,6 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a)
}
tcg_gen_ctpop_tl(t0, t0);
gen_store_gpr(t0, a->rd);
- tcg_temp_free(t0);
-
return true;
}
@@ -167,10 +151,6 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
} else {
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
}
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-
return true;
}
@@ -194,8 +174,5 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
} else {
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
}
-
- tcg_temp_free(t0);
-
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 06/91] target/mips: Drop tcg_temp_free from translate_addr_const.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 05/91] target/mips: Drop tcg_temp_free from octeon_translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 07/91] target/mips: Drop tcg_temp_free from tx79_translate.c Richard Henderson
` (85 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate_addr_const.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c
index 96f483418e..a510da406c 100644
--- a/target/mips/tcg/translate_addr_const.c
+++ b/target/mips/tcg/translate_addr_const.c
@@ -30,10 +30,6 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
-
return true;
}
@@ -54,8 +50,5 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t1);
- tcg_temp_free(t0);
-
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 07/91] target/mips: Drop tcg_temp_free from tx79_translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 06/91] target/mips: Drop tcg_temp_free from translate_addr_const.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 08/91] target/mips: Drop tcg_temp_free from vr54xx_translate.c Richard Henderson
` (84 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/tx79_translate.c | 41 --------------------------------
1 file changed, 41 deletions(-)
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 4e479c2d10..d46bc73972 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_r *a,
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
-
- tcg_temp_free(bx);
- tcg_temp_free(ax);
-
return true;
}
@@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
}
-
- tcg_temp_free(t2);
- tcg_temp_free(t1);
- tcg_temp_free(t0);
- tcg_temp_free(bx);
- tcg_temp_free(ax);
- tcg_temp_free(c1);
- tcg_temp_free(c0);
-
return true;
}
@@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
gen_store_gpr_hi(t0, a->rt);
-
- tcg_temp_free(t0);
- tcg_temp_free(addr);
-
return true;
}
@@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
-
- tcg_temp_free(addr);
- tcg_temp_free(t0);
-
return true;
}
@@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(t0, a->rs); /* a1 */
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
-
- tcg_temp_free(t0);
- tcg_temp_free(b0);
- tcg_temp_free(a0);
-
return true;
}
@@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen)
tcg_gen_shri_i64(bx, bx, wlen);
tcg_gen_shri_i64(ax, ax, wlen);
}
-
- tcg_temp_free(bx);
- tcg_temp_free(ax);
-
return true;
}
@@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a)
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
-
- tcg_temp_free(bx);
- tcg_temp_free(ax);
-
return true;
}
@@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
-
- tcg_temp_free(bx);
- tcg_temp_free(ax);
-
return true;
}
@@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a)
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
-
- tcg_temp_free(ax);
-
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 08/91] target/mips: Drop tcg_temp_free from vr54xx_translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (6 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 07/91] target/mips: Drop tcg_temp_free from tx79_translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 09/91] target/mips: Drop tcg_temp_free from translate.c Richard Henderson
` (83 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/vr54xx_translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c
index a7d241e4e7..804672f84c 100644
--- a/target/mips/tcg/vr54xx_translate.c
+++ b/target/mips/tcg/vr54xx_translate.c
@@ -49,10 +49,6 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
gen_helper_mult_acc(t0, cpu_env, t0, t1);
gen_store_gpr(t0, a->rd);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 09/91] target/mips: Drop tcg_temp_free from translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (7 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 08/91] target/mips: Drop tcg_temp_free from vr54xx_translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 10/91] target/s390x: Drop free_compare Richard Henderson
` (82 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 537 +-----------------------------------
1 file changed, 14 insertions(+), 523 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 24993bc97d..0fa9634d39 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1274,11 +1274,8 @@ static inline void gen_load_srsgpr(int from, int to)
tcg_gen_add_ptr(addr, cpu_env, addr);
tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
- tcg_temp_free_ptr(addr);
- tcg_temp_free_i32(t2);
}
gen_store_gpr(t0, to);
- tcg_temp_free(t0);
}
static inline void gen_store_srsgpr(int from, int to)
@@ -1297,9 +1294,6 @@ static inline void gen_store_srsgpr(int from, int to)
tcg_gen_add_ptr(addr, cpu_env, addr);
tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
- tcg_temp_free_ptr(addr);
- tcg_temp_free_i32(t2);
- tcg_temp_free(t0);
}
}
@@ -1396,7 +1390,6 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
t64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t64, t);
tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
- tcg_temp_free_i64(t64);
}
static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
@@ -1414,7 +1407,6 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t64, t);
tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
- tcg_temp_free_i64(t64);
} else {
gen_store_fpr32(ctx, t, reg | 1);
}
@@ -1439,7 +1431,6 @@ void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
t0 = tcg_temp_new_i64();
tcg_gen_shri_i64(t0, t, 32);
tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
- tcg_temp_free_i64(t0);
}
}
@@ -1852,8 +1843,6 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
default: \
abort(); \
} \
- tcg_temp_free_i##bits(fp0); \
- tcg_temp_free_i##bits(fp1); \
}
FOP_CONDS(, 0, d, FMT_D, 64)
@@ -1946,8 +1935,6 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
abort(); \
} \
STORE; \
- tcg_temp_free_i ## bits(fp0); \
- tcg_temp_free_i ## bits(fp1); \
}
FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
@@ -1967,7 +1954,6 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
- tcg_temp_free(t0); \
}
#else
#define OP_LD_ATOMIC(insn, fname) \
@@ -2065,9 +2051,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
tcg_gen_andc_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
gen_store_gpr(t0, rt);
break;
case OPC_LDR:
@@ -2090,15 +2074,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
gen_store_gpr(t0, rt);
break;
case OPC_LDPC:
t1 = tcg_const_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_temp_free(t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t0, rt);
break;
@@ -2106,7 +2087,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWPC:
t1 = tcg_const_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_temp_free(t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
gen_store_gpr(t0, rt);
break;
@@ -2170,9 +2150,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
tcg_gen_andc_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, rt);
break;
@@ -2199,9 +2177,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, rt);
break;
@@ -2214,7 +2190,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, rt);
break;
}
- tcg_temp_free(t0);
}
/* Store */
@@ -2273,8 +2248,6 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
gen_helper_0e2i(swr, t1, t0, mem_idx);
break;
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
@@ -2291,7 +2264,6 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
/* compare the address against that of the preceding LL */
gen_base_offset_addr(ctx, addr, base, offset);
tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
- tcg_temp_free(addr);
tcg_gen_movi_tl(t0, 0);
gen_store_gpr(t0, rt);
tcg_gen_br(done);
@@ -2304,10 +2276,8 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo);
tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval);
gen_store_gpr(t0, rt);
- tcg_temp_free(val);
gen_set_label(done);
- tcg_temp_free(t0);
}
/* Load and store */
@@ -2325,7 +2295,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, ft);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_SWC1:
@@ -2334,7 +2303,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
gen_load_fpr32(ctx, fp0, ft);
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_LDC1:
@@ -2343,7 +2311,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_SDC1:
@@ -2352,7 +2319,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
gen_load_fpr64(ctx, fp0, ft);
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
- tcg_temp_free_i64(fp0);
}
break;
default:
@@ -2381,7 +2347,6 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
- tcg_temp_free(t0);
}
/* Arithmetic with immediate operand */
@@ -2412,15 +2377,12 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
tcg_gen_xori_tl(t1, t1, ~uimm);
tcg_gen_xori_tl(t2, t0, uimm);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
- tcg_temp_free(t1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, rt);
- tcg_temp_free(t0);
}
break;
case OPC_ADDIU:
@@ -2445,14 +2407,11 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
tcg_gen_xori_tl(t1, t1, ~uimm);
tcg_gen_xori_tl(t2, t0, uimm);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
- tcg_temp_free(t1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rt);
- tcg_temp_free(t0);
}
break;
case OPC_DADDIU:
@@ -2535,7 +2494,6 @@ static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
break;
}
- tcg_temp_free(t0);
}
/* Shifts with immediate operand */
@@ -2575,7 +2533,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
tcg_gen_trunc_tl_i32(t1, t0);
tcg_gen_rotri_i32(t1, t1, uimm);
tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
- tcg_temp_free_i32(t1);
} else {
tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
}
@@ -2611,7 +2568,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
break;
#endif
}
- tcg_temp_free(t0);
}
/* Arithmetic */
@@ -2642,14 +2598,11 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
tcg_gen_xor_tl(t1, t1, t2);
tcg_gen_xor_tl(t2, t0, t2);
tcg_gen_andc_tl(t1, t2, t1);
- tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
- tcg_temp_free(t1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
}
break;
case OPC_ADDU:
@@ -2678,9 +2631,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
tcg_gen_xor_tl(t2, t1, t2);
tcg_gen_xor_tl(t1, t0, t1);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
- tcg_temp_free(t1);
/*
* operands of different sign, first operand and the result
* of different sign
@@ -2688,7 +2639,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
}
break;
case OPC_SUBU:
@@ -2718,14 +2668,11 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
tcg_gen_xor_tl(t1, t1, t2);
tcg_gen_xor_tl(t2, t0, t2);
tcg_gen_andc_tl(t1, t2, t1);
- tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
- tcg_temp_free(t1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
}
break;
case OPC_DADDU:
@@ -2752,9 +2699,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
tcg_gen_xor_tl(t2, t1, t2);
tcg_gen_xor_tl(t1, t0, t1);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
- tcg_temp_free(t1);
/*
* Operands of different sign, first operand and result different
* sign.
@@ -2762,7 +2707,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
}
break;
case OPC_DSUBU:
@@ -2818,9 +2762,6 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc,
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
break;
}
- tcg_temp_free(t2);
- tcg_temp_free(t1);
- tcg_temp_free(t0);
}
/* Logic */
@@ -2899,8 +2840,6 @@ static void gen_slt(DisasContext *ctx, uint32_t opc,
tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
break;
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* Shifts */
@@ -2947,8 +2886,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_gen_andi_i32(t2, t2, 0x1f);
tcg_gen_rotr_i32(t2, t3, t2);
tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
#if defined(TARGET_MIPS64)
@@ -2970,8 +2907,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
break;
#endif
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* Arithmetic on HI/LO registers */
@@ -3044,7 +2979,6 @@ static inline void gen_r6_ld(target_long addr, int reg, int memidx,
TCGv t0 = tcg_const_tl(addr);
tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
gen_store_gpr(t0, reg);
- tcg_temp_free(t0);
}
static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
@@ -3141,8 +3075,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_MOD:
@@ -3160,8 +3092,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_DIVU:
@@ -3173,8 +3103,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_MODU:
@@ -3186,8 +3114,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_MUL:
@@ -3198,8 +3124,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_mul_i32(t2, t2, t3);
tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case R6_OPC_MUH:
@@ -3210,8 +3134,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_muls2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case R6_OPC_MULU:
@@ -3222,8 +3144,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_mul_i32(t2, t2, t3);
tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case R6_OPC_MUHU:
@@ -3234,8 +3154,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_mulu2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
#if defined(TARGET_MIPS64)
@@ -3251,8 +3169,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_movi_tl(t3, 0);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_DMOD:
@@ -3267,8 +3183,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_movi_tl(t3, 0);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_DDIVU:
@@ -3277,8 +3191,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
TCGv t3 = tcg_const_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_DMODU:
@@ -3287,8 +3199,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
TCGv t3 = tcg_const_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case R6_OPC_DMUL:
@@ -3298,7 +3208,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
{
TCGv t2 = tcg_temp_new();
tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
- tcg_temp_free(t2);
}
break;
case R6_OPC_DMULU:
@@ -3308,18 +3217,14 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
{
TCGv t2 = tcg_temp_new();
tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
- tcg_temp_free(t2);
}
break;
#endif
default:
MIPS_INVAL("r6 mul/div");
gen_reserved_instruction(ctx);
- goto out;
+ break;
}
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
#if defined(TARGET_MIPS64)
@@ -3351,8 +3256,6 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
tcg_gen_rem_tl(cpu_HI[1], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case MMI_OPC_DIVU1:
@@ -3366,18 +3269,13 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
tcg_gen_remu_tl(cpu_HI[1], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
default:
MIPS_INVAL("div1 TX79");
gen_reserved_instruction(ctx);
- goto out;
+ break;
}
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
#endif
@@ -3414,8 +3312,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case OPC_DIVU:
@@ -3429,8 +3325,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case OPC_MULT:
@@ -3442,8 +3336,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_muls2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case OPC_MULTU:
@@ -3455,8 +3347,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_mulu2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
#if defined(TARGET_MIPS64)
@@ -3473,8 +3363,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_div_tl(cpu_LO[acc], t0, t1);
tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case OPC_DDIVU:
@@ -3484,8 +3372,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
}
break;
case OPC_DMULT:
@@ -3505,10 +3391,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case OPC_MADDU:
@@ -3523,10 +3407,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case OPC_MSUB:
@@ -3539,10 +3421,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
case OPC_MSUBU:
@@ -3557,20 +3437,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
- tcg_temp_free_i64(t2);
}
break;
default:
MIPS_INVAL("mul/div");
gen_reserved_instruction(ctx);
- goto out;
+ break;
}
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/*
@@ -3625,8 +3500,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
}
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case MMI_OPC_MULTU1:
@@ -3644,8 +3517,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
}
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
}
break;
case MMI_OPC_MADD1:
@@ -3661,13 +3532,11 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
if (rd) {
gen_move_low32(cpu_gpr[rd], t2);
}
- tcg_temp_free_i64(t2);
}
break;
case MMI_OPC_MADDU1:
@@ -3685,24 +3554,18 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
if (rd) {
gen_move_low32(cpu_gpr[rd], t2);
}
- tcg_temp_free_i64(t2);
}
break;
default:
MIPS_INVAL("mul/madd TXx9");
gen_reserved_instruction(ctx);
- goto out;
+ break;
}
-
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_cl(DisasContext *ctx, uint32_t opc,
@@ -3924,9 +3787,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
break;
#endif
}
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* Loongson multimedia instructions */
@@ -4221,7 +4081,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
tcg_gen_xor_i64(t1, t1, t2);
tcg_gen_xor_i64(t2, t2, t0);
tcg_gen_andc_i64(t1, t2, t1);
- tcg_temp_free_i64(t2);
tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(lab);
@@ -4242,7 +4101,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
tcg_gen_xor_i64(t1, t1, t2);
tcg_gen_xor_i64(t2, t2, t0);
tcg_gen_and_i64(t1, t1, t2);
- tcg_temp_free_i64(t2);
tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(lab);
@@ -4284,12 +4142,8 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
tcg_gen_extrl_i64_i32(t32, t64);
tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32,
get_fp_bit(cc), 1);
-
- tcg_temp_free_i32(t32);
- tcg_temp_free_i64(t64);
}
- goto no_rd;
- break;
+ return;
default:
MIPS_INVAL("loongson_cp2");
gen_reserved_instruction(ctx);
@@ -4297,10 +4151,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
}
gen_store_fpr64(ctx, t0, rd);
-
-no_rd:
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
}
static void gen_loongson_lswc2(DisasContext *ctx, int rt,
@@ -4328,7 +4178,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rt);
gen_store_gpr(t0, lsq_rt1);
- tcg_temp_free(t1);
break;
case OPC_GSLQC1:
check_cp1_enabled(ctx);
@@ -4341,7 +4190,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t1, rt);
gen_store_fpr64(ctx, t0, lsq_rt1);
- tcg_temp_free(t1);
break;
case OPC_GSSQ:
t1 = tcg_temp_new();
@@ -4353,7 +4201,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_gpr(t1, lsq_rt1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
- tcg_temp_free(t1);
break;
case OPC_GSSQC1:
check_cp1_enabled(ctx);
@@ -4366,7 +4213,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr64(ctx, t1, lsq_rt1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
- tcg_temp_free(t1);
break;
#endif
case OPC_GSSHFL:
@@ -4390,16 +4236,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t1, fp0);
tcg_gen_andc_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
#if defined(TARGET_MIPS64)
tcg_gen_extrl_i64_i32(fp0, t0);
#else
tcg_gen_ext32s_tl(fp0, t0);
#endif
gen_store_fpr32(ctx, fp0, rt);
- tcg_temp_free_i32(fp0);
break;
case OPC_GSLWRC1:
check_cp1_enabled(ctx);
@@ -4421,16 +4264,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t1, fp0);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
#if defined(TARGET_MIPS64)
tcg_gen_extrl_i64_i32(fp0, t0);
#else
tcg_gen_ext32s_tl(fp0, t0);
#endif
gen_store_fpr32(ctx, fp0, rt);
- tcg_temp_free_i32(fp0);
break;
#if defined(TARGET_MIPS64)
case OPC_GSLDLC1:
@@ -4450,9 +4290,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
tcg_gen_shl_tl(t2, t2, t1);
gen_load_fpr64(ctx, t1, rt);
tcg_gen_andc_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
gen_store_fpr64(ctx, t0, rt);
break;
case OPC_GSLDRC1:
@@ -4473,9 +4311,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
tcg_gen_shl_tl(t2, t2, t1);
gen_load_fpr64(ctx, t1, rt);
tcg_gen_and_tl(t1, t1, t2);
- tcg_temp_free(t2);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t1);
gen_store_fpr64(ctx, t0, rt);
break;
#endif
@@ -4495,8 +4331,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t1, fp0);
gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
- tcg_temp_free_i32(fp0);
- tcg_temp_free(t1);
break;
case OPC_GSSWRC1:
check_cp1_enabled(ctx);
@@ -4506,8 +4340,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t1, fp0);
gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
- tcg_temp_free_i32(fp0);
- tcg_temp_free(t1);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDLC1:
@@ -4516,7 +4348,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
gen_load_fpr64(ctx, t1, rt);
gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
- tcg_temp_free(t1);
break;
case OPC_GSSDRC1:
check_cp1_enabled(ctx);
@@ -4524,7 +4355,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
gen_load_fpr64(ctx, t1, rt);
gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
- tcg_temp_free(t1);
break;
#endif
default:
@@ -4538,7 +4368,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_reserved_instruction(ctx);
break;
}
- tcg_temp_free(t0);
}
/* Loongson EXT LDC2/SDC2 */
@@ -4633,7 +4462,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, rt);
- tcg_temp_free_i32(fp0);
break;
#if defined(TARGET_MIPS64)
case OPC_GSLDXC1:
@@ -4650,21 +4478,18 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
- tcg_temp_free(t1);
break;
case OPC_GSSHX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
ctx->default_tcg_memop_mask);
- tcg_temp_free(t1);
break;
case OPC_GSSWX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
- tcg_temp_free(t1);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDX:
@@ -4672,7 +4497,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
- tcg_temp_free(t1);
break;
#endif
case OPC_GSSWXC1:
@@ -4680,7 +4504,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
- tcg_temp_free_i32(fp0);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDXC1:
@@ -4688,14 +4511,11 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_load_fpr64(ctx, t1, rt);
tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
- tcg_temp_free(t1);
break;
#endif
default:
break;
}
-
- tcg_temp_free(t0);
}
/* Traps */
@@ -4805,8 +4625,6 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
generate_exception(ctx, EXCP_TRAP);
gen_set_label(l1);
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
@@ -5080,8 +4898,6 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
if (insn_bytes == 2) {
ctx->hflags |= MIPS_HFLAG_B16;
}
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
@@ -5150,13 +4966,9 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
fail:
MIPS_INVAL("bitops");
gen_reserved_instruction(ctx);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
return;
}
gen_store_gpr(t0, rt);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
@@ -5181,8 +4993,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
tcg_gen_and_tl(t0, t0, t2);
tcg_gen_shli_tl(t0, t0, 8);
tcg_gen_or_tl(t0, t0, t1);
- tcg_temp_free(t2);
- tcg_temp_free(t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
}
break;
@@ -5203,8 +5013,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
tcg_gen_and_tl(t0, t0, t2);
tcg_gen_shli_tl(t0, t0, 8);
tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t2);
- tcg_temp_free(t1);
}
break;
case OPC_DSHD:
@@ -5220,18 +5028,14 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
tcg_gen_shri_tl(t1, t0, 32);
tcg_gen_shli_tl(t0, t0, 32);
tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
- tcg_temp_free(t2);
- tcg_temp_free(t1);
}
break;
#endif
default:
MIPS_INVAL("bsfhl");
gen_reserved_instruction(ctx);
- tcg_temp_free(t0);
return;
}
- tcg_temp_free(t0);
}
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
@@ -5270,7 +5074,6 @@ static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
tcg_gen_concat_tl_i64(t2, t1, t0);
tcg_gen_shri_i64(t2, t2, 32 - bits);
gen_move_low32(cpu_gpr[rd], t2);
- tcg_temp_free_i64(t2);
}
break;
#if defined(TARGET_MIPS64)
@@ -5281,10 +5084,7 @@ static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
break;
#endif
}
- tcg_temp_free(t1);
}
-
- tcg_temp_free(t0);
}
void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp)
@@ -5311,7 +5111,6 @@ static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
break;
#endif
}
- tcg_temp_free(t0);
}
#ifndef CONFIG_USER_ONLY
@@ -5329,8 +5128,6 @@ static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
tcg_gen_concat32_i64(t1, t1, t0);
#endif
tcg_gen_st_i64(t1, cpu_env, off);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t0);
}
static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
@@ -5342,8 +5139,6 @@ static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
tcg_gen_ld_i64(t1, cpu_env, off);
tcg_gen_concat32_i64(t1, t1, t0);
tcg_gen_st_i64(t1, cpu_env, off);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t0);
}
static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
@@ -5357,7 +5152,6 @@ static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
tcg_gen_shri_i64(t0, t0, 32);
#endif
gen_move_low32(arg, t0);
- tcg_temp_free_i64(t0);
}
static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
@@ -5367,7 +5161,6 @@ static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
tcg_gen_ld_i64(t0, cpu_env, off);
tcg_gen_shri_i64(t0, t0, 32 + shift);
gen_move_low32(arg, t0);
- tcg_temp_free_i64(t0);
}
static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
@@ -5376,7 +5169,6 @@ static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
tcg_gen_ld_i32(t0, cpu_env, off);
tcg_gen_ext_i32_tl(arg, t0);
- tcg_temp_free_i32(t0);
}
static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
@@ -5391,7 +5183,6 @@ static inline void gen_mtc0_store32(TCGv arg, target_ulong off)
tcg_gen_trunc_tl_i32(t0, arg);
tcg_gen_st_i32(t0, cpu_env, off);
- tcg_temp_free_i32(t0);
}
#define CP0_CHECK(c) \
@@ -5713,7 +5504,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
#endif
gen_move_low32(arg, tmp);
- tcg_temp_free_i64(tmp);
}
register_name = "EntryLo0";
break;
@@ -5771,7 +5561,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
#endif
gen_move_low32(arg, tmp);
- tcg_temp_free_i64(tmp);
}
register_name = "EntryLo1";
break;
@@ -6300,7 +6089,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
gen_move_low32(arg, tmp);
- tcg_temp_free_i64(tmp);
}
register_name = "TagLo";
break;
@@ -8821,13 +8609,11 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free_i32(fp0);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free_i32(fp0);
}
break;
case 3:
@@ -8844,11 +8630,9 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
}
trace_mips_translate_tr("mftr", rt, u, sel, h);
gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
return;
die:
- tcg_temp_free(t0);
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
gen_reserved_instruction(ctx);
}
@@ -9025,13 +8809,11 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, rd);
- tcg_temp_free_i32(fp0);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(ctx, fp0, rd);
- tcg_temp_free_i32(fp0);
}
break;
case 3:
@@ -9049,11 +8831,9 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
}
}
trace_mips_translate_tr("mttr", rd, u, sel, h);
- tcg_temp_free(t0);
return;
die:
- tcg_temp_free(t0);
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
gen_reserved_instruction(ctx);
}
@@ -9079,7 +8859,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rt);
gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
- tcg_temp_free(t0);
}
opn = "mtc0";
break;
@@ -9100,7 +8879,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rt);
gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
- tcg_temp_free(t0);
}
opn = "dmtc0";
break;
@@ -9120,7 +8898,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
- tcg_temp_free(t0);
}
opn = "mthc0";
break;
@@ -9254,7 +9031,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
if (cc != 0) {
@@ -9294,7 +9071,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
tcg_gen_nand_i32(t0, t0, t1);
- tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
}
@@ -9305,7 +9081,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
tcg_gen_or_i32(t0, t0, t1);
- tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
}
@@ -9320,7 +9095,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
tcg_gen_nand_i32(t0, t0, t1);
- tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
}
@@ -9335,7 +9109,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
tcg_gen_or_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
tcg_gen_or_i32(t0, t0, t1);
- tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
}
@@ -9345,12 +9118,10 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
default:
MIPS_INVAL("cp1 cond branch");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
ctx->btarget = btarget;
ctx->hflags |= MIPS_HFLAG_BDS32;
- out:
- tcg_temp_free_i32(t0);
}
/* R6 CP1 Branches */
@@ -9367,7 +9138,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
"\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
gen_load_fpr64(ctx, t0, ft);
@@ -9387,7 +9158,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
default:
MIPS_INVAL("cp1 cond branch");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
tcg_gen_trunc_i64_tl(bcond, t0);
@@ -9402,9 +9173,6 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
ctx->hflags |= MIPS_HFLAG_BDS32;
break;
}
-
-out:
- tcg_temp_free_i64(t0);
}
/* Coprocessor 1 (FPU) */
@@ -9632,7 +9400,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
gen_load_fpr32(ctx, fp0, fs);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free_i32(fp0);
}
gen_store_gpr(t0, rt);
break;
@@ -9643,7 +9410,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fs);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_CFC1:
@@ -9673,7 +9439,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
gen_load_fpr32h(ctx, fp0, fs);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free_i32(fp0);
}
gen_store_gpr(t0, rt);
break;
@@ -9684,17 +9449,13 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(ctx, fp0, fs);
- tcg_temp_free_i32(fp0);
}
break;
default:
MIPS_INVAL("cp1 move");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
-
- out:
- tcg_temp_free(t0);
}
static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
@@ -9718,7 +9479,6 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
- tcg_temp_free_i32(t0);
gen_load_gpr(cpu_gpr[rd], rs);
gen_set_label(l1);
}
@@ -9741,7 +9501,6 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
gen_load_fpr32(ctx, t0, fs);
gen_store_fpr32(ctx, t0, fd);
gen_set_label(l1);
- tcg_temp_free_i32(t0);
}
static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
@@ -9760,11 +9519,9 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
- tcg_temp_free_i32(t0);
fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
gen_set_label(l1);
}
@@ -9792,7 +9549,6 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
tcg_gen_brcondi_i32(cond, t0, 0, l2);
gen_load_fpr32h(ctx, t0, fs);
gen_store_fpr32h(ctx, t0, fd);
- tcg_temp_free_i32(t0);
gen_set_label(l2);
}
@@ -9827,10 +9583,6 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp2);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(t1);
}
static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
@@ -9864,10 +9616,6 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp2);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(t1);
}
static void gen_farith(DisasContext *ctx, enum fopcode op1,
@@ -9883,9 +9631,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_SUB_S:
@@ -9896,9 +9642,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_MUL_S:
@@ -9909,9 +9653,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_DIV_S:
@@ -9922,9 +9664,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_SQRT_S:
@@ -9934,7 +9674,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_ABS_S:
@@ -9948,7 +9687,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_abs_s(fp0, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_MOV_S:
@@ -9957,7 +9695,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_NEG_S:
@@ -9971,7 +9708,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_chs_s(fp0, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_ROUND_L_S:
@@ -9986,9 +9722,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_round_l_s(fp64, cpu_env, fp32);
}
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_TRUNC_L_S:
@@ -10003,9 +9737,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
}
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_CEIL_L_S:
@@ -10020,9 +9752,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
}
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_FLOOR_L_S:
@@ -10037,9 +9767,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
}
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_ROUND_W_S:
@@ -10053,7 +9781,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_round_w_s(fp0, cpu_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_TRUNC_W_S:
@@ -10067,7 +9794,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_CEIL_W_S:
@@ -10081,7 +9807,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_FLOOR_W_S:
@@ -10095,7 +9820,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_SEL_S:
@@ -10126,7 +9850,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
gen_set_label(l1);
}
break;
@@ -10141,7 +9864,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
gen_set_label(l1);
}
}
@@ -10153,7 +9875,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_recip_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_RSQRT_S:
@@ -10163,7 +9884,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_MADDF_S:
@@ -10177,9 +9897,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp2, fd);
gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_MSUBF_S:
@@ -10193,9 +9910,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp2, fd);
gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_RINT_S:
@@ -10205,7 +9919,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_rint_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_CLASS_S:
@@ -10215,7 +9928,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_class_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_MIN_S: /* OPC_RECIP2_S */
@@ -10228,9 +9940,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
} else {
/* OPC_RECIP2_S */
check_cp1_64bitmode(ctx);
@@ -10241,9 +9950,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
}
break;
@@ -10257,9 +9964,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
} else {
/* OPC_RECIP1_S */
check_cp1_64bitmode(ctx);
@@ -10269,7 +9973,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_recip1_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
}
break;
@@ -10282,8 +9985,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
gen_store_fpr32(ctx, fp1, fd);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
} else {
/* OPC_RSQRT1_S */
check_cp1_64bitmode(ctx);
@@ -10293,7 +9994,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
}
break;
@@ -10306,8 +10006,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
gen_store_fpr32(ctx, fp1, fd);
- tcg_temp_free_i32(fp1);
- tcg_temp_free_i32(fp0);
} else {
/* OPC_RSQRT2_S */
check_cp1_64bitmode(ctx);
@@ -10318,9 +10016,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
}
break;
@@ -10332,9 +10028,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_CVT_W_S:
@@ -10348,7 +10042,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_CVT_L_S:
@@ -10363,9 +10056,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
}
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_CVT_PS_S:
@@ -10378,10 +10069,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32_0, fs);
gen_load_fpr32(ctx, fp32_1, ft);
tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
- tcg_temp_free_i32(fp32_1);
- tcg_temp_free_i32(fp32_0);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_CMP_F_S:
@@ -10416,9 +10104,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_SUB_D:
@@ -10430,9 +10116,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MUL_D:
@@ -10444,9 +10128,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_DIV_D:
@@ -10458,9 +10140,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_SQRT_D:
@@ -10471,7 +10151,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_ABS_D:
@@ -10486,7 +10165,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_abs_d(fp0, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MOV_D:
@@ -10496,7 +10174,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_NEG_D:
@@ -10511,7 +10188,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_chs_d(fp0, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_ROUND_L_D:
@@ -10526,7 +10202,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_round_l_d(fp0, cpu_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_TRUNC_L_D:
@@ -10541,7 +10216,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_CEIL_L_D:
@@ -10556,7 +10230,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_FLOOR_L_D:
@@ -10571,7 +10244,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_ROUND_W_D:
@@ -10586,9 +10258,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_round_w_d(fp32, cpu_env, fp64);
}
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_TRUNC_W_D:
@@ -10603,9 +10273,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
}
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_CEIL_W_D:
@@ -10620,9 +10288,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
}
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_FLOOR_W_D:
@@ -10637,9 +10303,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
}
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_SEL_D:
@@ -10670,7 +10334,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
gen_set_label(l1);
}
break;
@@ -10685,7 +10348,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
gen_set_label(l1);
}
}
@@ -10698,7 +10360,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_recip_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_RSQRT_D:
@@ -10709,7 +10370,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MADDF_D:
@@ -10723,9 +10383,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp2, fd);
gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MSUBF_D:
@@ -10739,9 +10396,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp2, fd);
gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_RINT_D:
@@ -10751,7 +10405,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_rint_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_CLASS_D:
@@ -10761,7 +10414,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_class_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MIN_D: /* OPC_RECIP2_D */
@@ -10773,8 +10425,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
} else {
/* OPC_RECIP2_D */
check_cp1_64bitmode(ctx);
@@ -10785,9 +10435,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
}
break;
@@ -10800,8 +10448,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
} else {
/* OPC_RECIP1_D */
check_cp1_64bitmode(ctx);
@@ -10811,7 +10457,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_recip1_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
}
break;
@@ -10824,8 +10469,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
} else {
/* OPC_RSQRT1_D */
check_cp1_64bitmode(ctx);
@@ -10835,7 +10478,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
}
break;
@@ -10848,8 +10490,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
- tcg_temp_free_i64(fp1);
- tcg_temp_free_i64(fp0);
} else {
/* OPC_RSQRT2_D */
check_cp1_64bitmode(ctx);
@@ -10860,9 +10500,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
}
break;
@@ -10897,9 +10535,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
gen_helper_float_cvts_d(fp32, cpu_env, fp64);
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_CVT_W_D:
@@ -10914,9 +10550,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
} else {
gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
}
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_CVT_L_D:
@@ -10931,7 +10565,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_CVT_S_W:
@@ -10941,7 +10574,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_cvts_w(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_CVT_D_W:
@@ -10952,9 +10584,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
- tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free_i64(fp64);
}
break;
case OPC_CVT_S_L:
@@ -10965,9 +10595,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
gen_helper_float_cvts_l(fp32, cpu_env, fp64);
- tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
- tcg_temp_free_i32(fp32);
}
break;
case OPC_CVT_D_L:
@@ -10978,7 +10606,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_CVT_PS_PW:
@@ -10989,7 +10616,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_ADD_PS:
@@ -11001,9 +10627,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_SUB_PS:
@@ -11015,9 +10639,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MUL_PS:
@@ -11029,9 +10651,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_ABS_PS:
@@ -11042,7 +10662,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_abs_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MOV_PS:
@@ -11052,7 +10671,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_NEG_PS:
@@ -11063,7 +10681,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_chs_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MOVCF_PS:
@@ -11082,7 +10699,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
gen_set_label(l1);
}
break;
@@ -11097,7 +10713,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
gen_set_label(l1);
}
}
@@ -11111,9 +10726,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_MULR_PS:
@@ -11125,9 +10738,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_RECIP2_PS:
@@ -11139,9 +10750,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_RECIP1_PS:
@@ -11152,7 +10761,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_RSQRT1_PS:
@@ -11163,7 +10771,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_RSQRT2_PS:
@@ -11175,9 +10782,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_CVT_S_PU:
@@ -11188,7 +10793,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp0, fs);
gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_CVT_PW_PS:
@@ -11199,7 +10803,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_CVT_S_PL:
@@ -11210,7 +10813,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_PLL_PS:
@@ -11223,8 +10825,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp1, ft);
gen_store_fpr32h(ctx, fp0, fd);
gen_store_fpr32(ctx, fp1, fd);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
}
break;
case OPC_PLU_PS:
@@ -11237,8 +10837,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp1, ft);
gen_store_fpr32(ctx, fp1, fd);
gen_store_fpr32h(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
}
break;
case OPC_PUL_PS:
@@ -11251,8 +10849,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp1, ft);
gen_store_fpr32(ctx, fp1, fd);
gen_store_fpr32h(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
}
break;
case OPC_PUU_PS:
@@ -11265,8 +10861,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp1, ft);
gen_store_fpr32(ctx, fp1, fd);
gen_store_fpr32h(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
}
break;
case OPC_CMP_F_PS:
@@ -11324,7 +10918,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fd);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_LDXC1:
@@ -11334,7 +10927,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_LUXC1:
@@ -11345,7 +10937,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_SWXC1:
@@ -11354,7 +10945,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
- tcg_temp_free_i32(fp0);
}
break;
case OPC_SDXC1:
@@ -11364,7 +10954,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
- tcg_temp_free_i64(fp0);
}
break;
case OPC_SUXC1:
@@ -11374,11 +10963,9 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
- tcg_temp_free_i64(fp0);
}
break;
}
- tcg_temp_free(t0);
}
static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
@@ -11405,7 +10992,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
- tcg_temp_free(t0);
if (cpu_is_bigendian(ctx)) {
gen_load_fpr32(ctx, fp, fs);
gen_load_fpr32h(ctx, fph, ft);
@@ -11418,8 +11004,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_store_fpr32h(ctx, fp, fd);
}
gen_set_label(l2);
- tcg_temp_free_i32(fp);
- tcg_temp_free_i32(fph);
}
break;
case OPC_MADD_S:
@@ -11433,10 +11017,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
}
break;
case OPC_MADD_D:
@@ -11451,10 +11032,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_MADD_PS:
@@ -11468,10 +11046,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_MSUB_S:
@@ -11485,10 +11060,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
}
break;
case OPC_MSUB_D:
@@ -11503,10 +11075,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_MSUB_PS:
@@ -11520,10 +11089,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_NMADD_S:
@@ -11537,10 +11103,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
}
break;
case OPC_NMADD_D:
@@ -11555,10 +11118,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_NMADD_PS:
@@ -11572,10 +11132,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_NMSUB_S:
@@ -11589,10 +11146,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
gen_store_fpr32(ctx, fp2, fd);
- tcg_temp_free_i32(fp2);
}
break;
case OPC_NMSUB_D:
@@ -11607,10 +11161,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
case OPC_NMSUB_PS:
@@ -11624,10 +11175,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
- tcg_temp_free_i64(fp0);
- tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free_i64(fp2);
}
break;
default:
@@ -11716,7 +11264,6 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_reserved_instruction(ctx);
break;
}
- tcg_temp_free(t0);
}
static inline void clear_branch_hflags(DisasContext *ctx)
@@ -11775,11 +11322,9 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
tcg_gen_andi_tl(t0, btarget, 0x1);
tcg_gen_trunc_tl_i32(t1, t0);
- tcg_temp_free(t0);
tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
tcg_gen_or_i32(hflags, hflags, t1);
- tcg_temp_free_i32(t1);
tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
} else {
@@ -11809,7 +11354,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
"\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
/* Load needed operands and calculate btarget */
@@ -11863,13 +11408,12 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
gen_load_gpr(tbase, rt);
gen_op_addr_add(ctx, btarget, tbase, toffset);
- tcg_temp_free(tbase);
}
break;
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
if (bcond_compute == 0) {
@@ -11890,7 +11434,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
/* Generating branch here as compact branches don't have delay slot */
@@ -11980,10 +11524,6 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
/* OPC_BNVC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
}
- tcg_temp_free(input_overflow);
- tcg_temp_free(t4);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
} else if (rs < rt && rs == 0) {
/* OPC_BEQZALC, OPC_BNEZALC */
if (opc == OPC_BEQZALC) {
@@ -12013,7 +11553,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Compact conditional branch/jump");
gen_reserved_instruction(ctx);
- goto out;
+ return;
}
/* Generating branch here as compact branches don't have delay slot */
@@ -12022,10 +11562,6 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
ctx->hflags |= MIPS_HFLAG_FBNSLOT;
}
-
-out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
void gen_addiupc(DisasContext *ctx, int rx, int imm,
@@ -12045,8 +11581,6 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
if (!is_64_bit) {
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
}
-
- tcg_temp_free(t0);
}
static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
@@ -12056,8 +11590,6 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
gen_helper_cache(cpu_env, t1, t0);
- tcg_temp_free(t1);
- tcg_temp_free_i32(t0);
}
static inline bool is_uhi(DisasContext *ctx, int sdbbp_code)
@@ -12085,9 +11617,6 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
gen_store_gpr(t1, rd);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_sync(int stype)
@@ -12191,7 +11720,6 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
break;
#endif
}
- tcg_temp_free(t0);
}
static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
@@ -12405,7 +11933,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
TCGv_i32 sa_t = tcg_const_i32(v2);
gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
- tcg_temp_free_i32(sa_t);
break;
}
case OPC_PRECR_SRA_R_PH_W:
@@ -12414,7 +11941,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
TCGv_i32 sa_t = tcg_const_i32(v2);
gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
- tcg_temp_free_i32(sa_t);
break;
}
case OPC_PRECRQ_PH_W:
@@ -12603,7 +12129,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
{
TCGv_i32 ret_t = tcg_const_i32(ret);
gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
- tcg_temp_free_i32(ret_t);
break;
}
case OPC_PRECR_SRA_R_QH_PW:
@@ -12611,7 +12136,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
{
TCGv_i32 sa_v = tcg_const_i32(ret);
gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
- tcg_temp_free_i32(sa_v);
break;
}
case OPC_PRECRQ_OB_QH:
@@ -12638,9 +12162,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
#endif
}
-
- tcg_temp_free(v1_t);
- tcg_temp_free(v2_t);
}
static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
@@ -12880,10 +12401,6 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
break;
#endif
}
-
- tcg_temp_free(t0);
- tcg_temp_free(v1_t);
- tcg_temp_free(v2_t);
}
static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
@@ -13190,10 +12707,6 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
#endif
}
-
- tcg_temp_free_i32(t0);
- tcg_temp_free(v1_t);
- tcg_temp_free(v2_t);
}
static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
@@ -13330,8 +12843,6 @@ static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
#endif
}
- tcg_temp_free(t0);
- tcg_temp_free(val_t);
}
static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
@@ -13514,10 +13025,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
break;
#endif
}
-
- tcg_temp_free(t1);
- tcg_temp_free(v1_t);
- tcg_temp_free(v2_t);
}
static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
@@ -13605,7 +13112,6 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
break;
#endif
}
- tcg_temp_free(t0);
}
static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
@@ -13822,10 +13328,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
#endif
}
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(v1_t);
}
/* End MIPSDSP functions. */
@@ -14676,9 +14178,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rs);
gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
break;
}
default: /* Invalid */
@@ -14948,9 +14447,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rs);
gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
break;
}
default: /* Invalid */
@@ -15177,8 +14673,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
gen_helper_fork(t0, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
break;
case OPC_YIELD:
@@ -15189,7 +14683,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rs);
gen_helper_yield(t0, cpu_env, t0);
gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
}
break;
default:
@@ -15432,7 +14925,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_reserved_instruction(ctx);
break;
}
- tcg_temp_free(t0);
}
#endif /* !CONFIG_USER_ONLY */
break;
@@ -15880,7 +15372,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
- tcg_temp_free(t0);
}
#else
gen_reserved_instruction(ctx);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 10/91] target/s390x: Drop free_compare
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (8 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 09/91] target/mips: Drop tcg_temp_free from translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 11/91] target/s390x: Drop tcg_temp_free from translate_vx.c.inc Richard Henderson
` (81 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, David Hildenbrand, Ilya Leoshkevich,
Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Remove the g1 and g2 members of DisasCompare, as they were
used to track which temps needed to be freed.
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 46 +-----------------------------------
1 file changed, 1 insertion(+), 45 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 21a57d5eb2..669671075e 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -156,8 +156,6 @@ struct DisasContext {
typedef struct {
TCGCond cond:8;
bool is_64;
- bool g1;
- bool g2;
union {
struct { TCGv_i64 a, b; } s64;
struct { TCGv_i32 a, b; } s32;
@@ -722,7 +720,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
c->u.s32.a = cc_op;
c->u.s32.b = cc_op;
- c->g1 = c->g2 = true;
c->is_64 = false;
return;
}
@@ -839,7 +836,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
/* Load up the arguments of the comparison. */
c->is_64 = true;
- c->g1 = c->g2 = false;
switch (old_cc_op) {
case CC_OP_LTGT0_32:
c->is_64 = false;
@@ -861,13 +857,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_FLOGR:
c->u.s64.a = cc_dst;
c->u.s64.b = tcg_constant_i64(0);
- c->g1 = true;
break;
case CC_OP_LTGT_64:
case CC_OP_LTUGTU_64:
c->u.s64.a = cc_src;
c->u.s64.b = cc_dst;
- c->g1 = c->g2 = true;
break;
case CC_OP_TM_32:
@@ -882,7 +876,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_SUBU:
c->is_64 = true;
c->u.s64.b = tcg_constant_i64(0);
- c->g1 = true;
switch (mask) {
case 8 | 2:
case 4 | 1: /* result */
@@ -900,7 +893,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_STATIC:
c->is_64 = false;
c->u.s32.a = cc_op;
- c->g1 = true;
switch (mask) {
case 0x8 | 0x4 | 0x2: /* cc != 3 */
cond = TCG_COND_NE;
@@ -916,7 +908,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
break;
case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
cond = TCG_COND_EQ;
- c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
@@ -935,7 +926,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
break;
case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
cond = TCG_COND_NE;
- c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
@@ -959,7 +949,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
default:
/* CC is masked by something else: (8 >> cc) & mask. */
cond = TCG_COND_NE;
- c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
@@ -974,24 +963,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
c->cond = cond;
}
-static void free_compare(DisasCompare *c)
-{
- if (!c->g1) {
- if (c->is_64) {
- tcg_temp_free_i64(c->u.s64.a);
- } else {
- tcg_temp_free_i32(c->u.s32.a);
- }
- }
- if (!c->g2) {
- if (c->is_64) {
- tcg_temp_free_i64(c->u.s64.b);
- } else {
- tcg_temp_free_i32(c->u.s32.b);
- }
- }
-}
-
/* ====================================================================== */
/* Define the insn format enumeration. */
#define F0(N) FMT_##N,
@@ -1302,7 +1273,6 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
}
egress:
- free_compare(c);
return ret;
}
@@ -1612,8 +1582,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
c.cond = TCG_COND_NE;
c.is_64 = false;
- c.g1 = false;
- c.g2 = false;
t = tcg_temp_new_i64();
tcg_gen_subi_i64(t, regs[r1], 1);
@@ -1635,8 +1603,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
c.cond = TCG_COND_NE;
c.is_64 = false;
- c.g1 = false;
- c.g2 = false;
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, regs[r1], 32);
@@ -1659,8 +1625,6 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
c.cond = TCG_COND_NE;
c.is_64 = true;
- c.g1 = true;
- c.g2 = false;
tcg_gen_subi_i64(regs[r1], regs[r1], 1);
c.u.s64.a = regs[r1];
@@ -1680,8 +1644,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
c.is_64 = false;
- c.g1 = false;
- c.g2 = false;
t = tcg_temp_new_i64();
tcg_gen_add_i64(t, regs[r1], regs[r3]);
@@ -1708,15 +1670,12 @@ static DisasJumpType op_bx64(DisasContext *s, DisasOps *o)
if (r1 == (r3 | 1)) {
c.u.s64.b = load_reg(r3 | 1);
- c.g2 = false;
} else {
c.u.s64.b = regs[r3 | 1];
- c.g2 = true;
}
tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
c.u.s64.a = regs[r1];
- c.g1 = true;
return help_branch(s, &c, is_imm, imm, o->in2);
}
@@ -1731,7 +1690,7 @@ static DisasJumpType op_cj(DisasContext *s, DisasOps *o)
if (s->insn->data) {
c.cond = tcg_unsigned_cond(c.cond);
}
- c.is_64 = c.g1 = c.g2 = true;
+ c.is_64 = true;
c.u.s64.a = o->in1;
c.u.s64.b = o->in2;
@@ -2925,13 +2884,11 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
if (c.is_64) {
tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
o->in2, o->in1);
- free_compare(&c);
} else {
TCGv_i32 t32 = tcg_temp_new_i32();
TCGv_i64 t, z;
tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
- free_compare(&c);
t = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t, t32);
@@ -4022,7 +3979,6 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
} else {
tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
}
- free_compare(&c);
r1 = get_field(s, r1);
a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 11/91] target/s390x: Drop tcg_temp_free from translate_vx.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (9 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 10/91] target/s390x: Drop free_compare Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 12/91] target/s390x: Drop tcg_temp_free from translate.c Richard Henderson
` (80 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, David Hildenbrand, Ilya Leoshkevich,
Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate_vx.c.inc | 143 ----------------------------
1 file changed, 143 deletions(-)
diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc
index 3fadc82e5c..43dfbfd03f 100644
--- a/target/s390x/tcg/translate_vx.c.inc
+++ b/target/s390x/tcg/translate_vx.c.inc
@@ -183,8 +183,6 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
/* generate the final ptr by adding cpu_env */
tcg_gen_trunc_i64_ptr(ptr, tmp);
tcg_gen_add_ptr(ptr, ptr, cpu_env);
-
- tcg_temp_free_i64(tmp);
}
#define gen_gvec_2(v1, v2, gen) \
@@ -272,13 +270,6 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
fn(dl, dh, al, ah, bl, bh);
write_vec_element_i64(dh, d, 0, ES_64);
write_vec_element_i64(dl, d, 1, ES_64);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(dl);
- tcg_temp_free_i64(ah);
- tcg_temp_free_i64(al);
- tcg_temp_free_i64(bh);
- tcg_temp_free_i64(bl);
}
typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
@@ -305,15 +296,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
fn(dl, dh, al, ah, bl, bh, cl, ch);
write_vec_element_i64(dh, d, 0, ES_64);
write_vec_element_i64(dl, d, 1, ES_64);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(dl);
- tcg_temp_free_i64(ah);
- tcg_temp_free_i64(al);
- tcg_temp_free_i64(bh);
- tcg_temp_free_i64(bl);
- tcg_temp_free_i64(ch);
- tcg_temp_free_i64(cl);
}
static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
@@ -351,7 +333,6 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -386,7 +367,6 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
write_vec_element_i64(t, get_field(s, v1), 0, ES_64);
tcg_gen_movi_i64(t, generate_byte_mask(i2));
write_vec_element_i64(t, get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(t);
}
return DISAS_NEXT;
}
@@ -427,8 +407,6 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ);
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -451,7 +429,6 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
gen_gvec_dup_i64(es, get_field(s, v1), tmp);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -469,7 +446,6 @@ static DisasJumpType op_vlebr(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es);
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -486,7 +462,6 @@ static DisasJumpType op_vlbrrep(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es);
gen_gvec_dup_i64(es, get_field(s, v1), tmp);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -518,7 +493,6 @@ static DisasJumpType op_vllebrz(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
write_vec_element_i64(tcg_constant_i64(0), get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -572,9 +546,6 @@ static DisasJumpType op_vlbr(DisasContext *s, DisasOps *o)
write:
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -592,7 +563,6 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -647,8 +617,6 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps *o)
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -688,8 +656,6 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
default:
g_assert_not_reached();
}
- tcg_temp_free_ptr(ptr);
-
return DISAS_NEXT;
}
@@ -730,7 +696,6 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
gen_gvec_dup_imm(es, get_field(s, v1), 0);
write_vec_element_i64(t, get_field(s, v1), enr, es);
- tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@@ -768,9 +733,6 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
/* Store the last element, loaded first */
write_vec_element_i64(t0, v1, 1, ES_64);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
@@ -794,8 +756,6 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
gen_helper_vll(cpu_env, a0, o->addr1, bytes);
- tcg_temp_free_i64(bytes);
- tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
@@ -835,8 +795,6 @@ static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
default:
g_assert_not_reached();
}
- tcg_temp_free_ptr(ptr);
-
return DISAS_NEXT;
}
@@ -856,7 +814,6 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
gen_helper_vll(cpu_env, a0, o->addr1, o->in2);
- tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
@@ -898,7 +855,6 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, v1, dst_idx, es);
}
}
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -974,7 +930,6 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
}
write_vec_element_i64(tmp, v1, dst_idx, dst_es);
}
- tcg_temp_free_i64(tmp);
} else {
gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]);
}
@@ -1004,8 +959,6 @@ static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
read_vec_element_i64(t1, get_field(s, v3), i3, ES_64);
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
@@ -1057,7 +1010,6 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1098,7 +1050,6 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN);
write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1116,7 +1067,6 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1134,7 +1084,6 @@ static DisasJumpType op_vstebr(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1189,9 +1138,6 @@ write:
tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_LEUQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_LEUQ);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -1209,7 +1155,6 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1251,9 +1196,6 @@ static DisasJumpType op_vster(DisasContext *s, DisasOps *o)
tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -1284,7 +1226,6 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
}
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
}
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1297,7 +1238,6 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
gen_helper_vstl(cpu_env, a0, o->addr1, o->in2);
- tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
@@ -1335,7 +1275,6 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, v1, dst_idx, dst_es);
}
}
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1377,10 +1316,6 @@ static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
/* Isolate and shift the carry into position */
tcg_gen_and_i64(d, d, msb_mask);
tcg_gen_shri_i64(d, d, msb_bit_nr);
-
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
- tcg_temp_free_i64(t3);
}
static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
@@ -1399,7 +1334,6 @@ static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_gen_add_i32(t, a, b);
tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b);
- tcg_temp_free_i32(t);
}
static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
@@ -1408,7 +1342,6 @@ static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
tcg_gen_add_i64(t, a, b);
tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b);
- tcg_temp_free_i64(t);
}
static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
@@ -1422,9 +1355,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
tcg_gen_mov_i64(dh, zero);
-
- tcg_temp_free_i64(th);
- tcg_temp_free_i64(tl);
}
static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
@@ -1460,8 +1390,6 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_extract_i64(tl, cl, 0, 1);
tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero);
-
- tcg_temp_free_i64(tl);
}
static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
@@ -1490,9 +1418,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
tcg_gen_mov_i64(dh, zero);
-
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
}
static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
@@ -1533,9 +1458,6 @@ static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_gen_addi_i64(t0, t0, 1);
tcg_gen_shri_i64(t0, t0, 1);
tcg_gen_extrl_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
@@ -1550,10 +1472,6 @@ static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
gen_addi2_i64(dl, dh, dl, dh, 1);
tcg_gen_extract2_i64(dl, dl, dh, 1);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(ah);
- tcg_temp_free_i64(bh);
}
static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
@@ -1586,9 +1504,6 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_gen_addi_i64(t0, t0, 1);
tcg_gen_shri_i64(t0, t0, 1);
tcg_gen_extrl_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
@@ -1599,8 +1514,6 @@ static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
gen_addi2_i64(dl, dh, dl, dh, 1);
tcg_gen_extract2_i64(dl, dl, dh, 1);
-
- tcg_temp_free_i64(dh);
}
static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
@@ -1635,9 +1548,6 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
}
gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
-
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(sum);
return DISAS_NEXT;
}
@@ -1682,9 +1592,6 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
read_vec_element_i64(high, get_field(s, v1), 0, ES_64);
read_vec_element_i64(low, get_field(s, v1), 1, ES_64);
gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
-
- tcg_temp_free_i64(low);
- tcg_temp_free_i64(high);
}
return DISAS_NEXT;
}
@@ -1853,8 +1760,6 @@ static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
tcg_gen_mul_i32(t0, a, b);
tcg_gen_add_i32(d, t0, c);
-
- tcg_temp_free_i32(t0);
}
static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
@@ -1869,10 +1774,6 @@ static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
tcg_gen_mul_i64(t0, t0, t1);
tcg_gen_add_i64(t0, t0, t2);
tcg_gen_extrh_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
}
static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
@@ -1887,10 +1788,6 @@ static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
tcg_gen_mul_i64(t0, t0, t1);
tcg_gen_add_i64(t0, t0, t2);
tcg_gen_extrh_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
}
static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
@@ -1974,7 +1871,6 @@ static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_muls2_i32(t, d, a, b);
- tcg_temp_free_i32(t);
}
static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
@@ -1982,7 +1878,6 @@ static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_mulu2_i32(t, d, a, b);
- tcg_temp_free_i32(t);
}
static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
@@ -2099,11 +1994,6 @@ static DisasJumpType op_vmsl(DisasContext *s, DisasOps *o)
/* Store final result into v1. */
write_vec_element_i64(h1, get_field(s, v1), 0, ES_64);
write_vec_element_i64(l1, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free_i64(l1);
- tcg_temp_free_i64(h1);
- tcg_temp_free_i64(l2);
- tcg_temp_free_i64(h2);
return DISAS_NEXT;
}
@@ -2169,8 +2059,6 @@ static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
tcg_gen_and_i32(t, t, b);
tcg_gen_andc_i32(d, d, b);
tcg_gen_or_i32(d, d, t);
-
- tcg_temp_free_i32(t);
}
static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
@@ -2181,8 +2069,6 @@ static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
tcg_gen_and_i64(t, t, b);
tcg_gen_andc_i64(d, d, b);
tcg_gen_or_i64(d, d, t);
-
- tcg_temp_free_i64(t);
}
static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
@@ -2291,7 +2177,6 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
default:
g_assert_not_reached();
}
- tcg_temp_free_i32(shift);
}
return DISAS_NEXT;
}
@@ -2311,7 +2196,6 @@ static DisasJumpType gen_vsh_by_byte(DisasContext *s, DisasOps *o,
read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
tcg_gen_andi_i64(shift, shift, byte ? 0x78 : 7);
gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), shift, 0, gen);
- tcg_temp_free_i64(shift);
}
return DISAS_NEXT;
}
@@ -2367,10 +2251,6 @@ static DisasJumpType op_vsld(DisasContext *s, DisasOps *o)
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
return DISAS_NEXT;
}
@@ -2397,10 +2277,6 @@ static DisasJumpType op_vsrd(DisasContext *s, DisasOps *o)
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
return DISAS_NEXT;
}
@@ -2445,9 +2321,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
/* "invert" the result: -1 -> 0; 0 -> 1 */
tcg_gen_addi_i64(dl, th, 1);
tcg_gen_mov_i64(dh, zero);
-
- tcg_temp_free_i64(th);
- tcg_temp_free_i64(tl);
}
static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
@@ -2482,8 +2355,6 @@ static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_not_i64(tl, bl);
tcg_gen_not_i64(th, bh);
gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch);
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
}
static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
@@ -2508,9 +2379,6 @@ static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_not_i64(tl, bl);
tcg_gen_not_i64(th, bh);
gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch);
-
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
}
static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
@@ -2550,8 +2418,6 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
}
write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64);
}
- tcg_temp_free_i64(sum);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -2580,10 +2446,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
}
write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64);
write_vec_element_i64(suml, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free_i64(sumh);
- tcg_temp_free_i64(suml);
- tcg_temp_free_i64(tmpl);
return DISAS_NEXT;
}
@@ -2611,8 +2473,6 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
}
write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32);
}
- tcg_temp_free_i32(sum);
- tcg_temp_free_i32(tmp);
return DISAS_NEXT;
}
@@ -3399,9 +3259,6 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
read_vec_element_i64(tmp, v2, 1, ES_64);
write_vec_element_i64(tmp, v1, 1, ES_64);
}
-
- tcg_temp_free_i64(tmp);
-
return DISAS_NEXT;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 12/91] target/s390x: Drop tcg_temp_free from translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (10 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 11/91] target/s390x: Drop tcg_temp_free from translate_vx.c.inc Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 13/91] target/s390x: Remove assert vs g_in2 Richard Henderson
` (79 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, David Hildenbrand, Ilya Leoshkevich,
Philippe Mathieu-Daudé
Translators are no longer required to free tcg temporaries.
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 105 -----------------------------------
1 file changed, 105 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 669671075e..954a1edd10 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -306,8 +306,6 @@ static TCGv_i128 load_freg_128(int reg)
TCGv_i128 r = tcg_temp_new_i128();
tcg_gen_concat_i64_i128(r, l, h);
- tcg_temp_free_i64(h);
- tcg_temp_free_i64(l);
return r;
}
@@ -1263,10 +1261,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
TCGv_i64 z = tcg_constant_i64(0);
tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
tcg_gen_extu_i32_i64(t1, t0);
- tcg_temp_free_i32(t0);
tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
per_branch_cond(s, TCG_COND_NE, t1, z);
- tcg_temp_free_i64(t1);
}
ret = DISAS_PC_UPDATED;
@@ -1525,7 +1521,6 @@ static void save_link_info(DisasContext *s, DisasOps *o)
tcg_gen_extu_i32_i64(t, cc_op);
tcg_gen_shli_i64(t, t, 28);
tcg_gen_or_i64(o->out, o->out, t);
- tcg_temp_free_i64(t);
}
static DisasJumpType op_bal(DisasContext *s, DisasOps *o)
@@ -1589,7 +1584,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
c.u.s32.a = tcg_temp_new_i32();
c.u.s32.b = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
- tcg_temp_free_i64(t);
return help_branch(s, &c, is_imm, imm, o->in2);
}
@@ -1611,7 +1605,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
c.u.s32.a = tcg_temp_new_i32();
c.u.s32.b = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
- tcg_temp_free_i64(t);
return help_branch(s, &c, 1, imm, o->in2);
}
@@ -1652,7 +1645,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
tcg_gen_extrl_i64_i32(c.u.s32.b, regs[r3 | 1]);
store_reg32_i64(r1, t);
- tcg_temp_free_i64(t);
return help_branch(s, &c, is_imm, imm, o->in2);
}
@@ -1971,11 +1963,9 @@ static DisasJumpType op_cksm(DisasContext *s, DisasOps *o)
gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]);
set_cc_static(s);
tcg_gen_extr_i128_i64(o->out, len, pair);
- tcg_temp_free_i128(pair);
tcg_gen_add_i64(regs[r2], regs[r2], len);
tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
- tcg_temp_free_i64(len);
return DISAS_NEXT;
}
@@ -2077,7 +2067,6 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps *o)
tcg_gen_extrl_i64_i32(t1, o->in1);
gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
set_cc_static(s);
- tcg_temp_free_i32(t1);
return DISAS_NEXT;
}
@@ -2087,7 +2076,6 @@ static DisasJumpType op_clst(DisasContext *s, DisasOps *o)
gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2);
tcg_gen_extr_i128_i64(o->in2, o->in1, pair);
- tcg_temp_free_i128(pair);
set_cc_static(s);
return DISAS_NEXT;
@@ -2099,7 +2087,6 @@ static DisasJumpType op_cps(DisasContext *s, DisasOps *o)
tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull);
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
tcg_gen_or_i64(o->out, o->out, t);
- tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@@ -2115,14 +2102,12 @@ static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
addr = get_address(s, 0, b2, d2);
tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1,
get_mem_index(s), s->insn->data | MO_ALIGN);
- tcg_temp_free_i64(addr);
/* Are the memory and expected values (un)equal? Note that this setcond
produces the output CC value, thus the NE sense of the test. */
cc = tcg_temp_new_i64();
tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out);
tcg_gen_extrl_i64_i32(cc_op, cc);
- tcg_temp_free_i64(cc);
set_cc_static(s);
return DISAS_NEXT;
@@ -2182,7 +2167,6 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE));
tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2,
get_mem_index(s), mop | MO_ALIGN);
- tcg_temp_free_i64(addr);
/* Are the memory and expected values (un)equal? */
cc = tcg_temp_new_i64();
@@ -2196,14 +2180,12 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
} else {
tcg_gen_mov_i64(o->out, old);
}
- tcg_temp_free_i64(old);
/* If the comparison was equal, and the LSB of R2 was set,
then we need to flush the TLB (for all cpus). */
tcg_gen_xori_i64(cc, cc, 1);
tcg_gen_and_i64(cc, cc, o->in2);
tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab);
- tcg_temp_free_i64(cc);
gen_helper_purge(cpu_env);
gen_set_label(lab);
@@ -2218,9 +2200,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
TCGv_i32 t2 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t2, o->in1);
gen_helper_cvd(t1, t2);
- tcg_temp_free_i32(t2);
tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
- tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
@@ -2322,7 +2302,6 @@ static DisasJumpType op_divs64(DisasContext *s, DisasOps *o)
gen_helper_divs64(t, cpu_env, o->in1, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, t);
- tcg_temp_free_i128(t);
return DISAS_NEXT;
}
@@ -2332,7 +2311,6 @@ static DisasJumpType op_divu64(DisasContext *s, DisasOps *o)
gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, t);
- tcg_temp_free_i128(t);
return DISAS_NEXT;
}
@@ -2387,8 +2365,6 @@ static DisasJumpType op_epsw(DisasContext *s, DisasOps *o)
if (r2 != 0) {
store_reg32_i64(r2, psw_mask);
}
-
- tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@@ -2528,7 +2504,6 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
tcg_gen_movi_i64(tmp, ccm);
gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -2551,8 +2526,6 @@ static DisasJumpType op_ipm(DisasContext *s, DisasOps *o)
tcg_gen_extu_i32_i64(t2, cc_op);
tcg_gen_deposit_i64(t1, t1, t2, 4, 60);
tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
return DISAS_NEXT;
}
@@ -2892,11 +2865,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
t = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t, t32);
- tcg_temp_free_i32(t32);
z = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
- tcg_temp_free_i64(t);
}
return DISAS_NEXT;
@@ -2953,8 +2924,6 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
/* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
tcg_gen_shli_i64(t1, t1, 32);
gen_helper_load_psw(cpu_env, t1, t2);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
return DISAS_NORETURN;
}
@@ -2971,8 +2940,6 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
gen_helper_load_psw(cpu_env, t1, t2);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
return DISAS_NORETURN;
}
#endif
@@ -2997,7 +2964,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32_i64(r1, t1);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -3012,8 +2978,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
- tcg_temp_free(t2);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -3026,9 +2990,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32_i64(r1, t1);
}
- tcg_temp_free(t2);
- tcg_temp_free(t1);
-
return DISAS_NEXT;
}
@@ -3043,7 +3004,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32h_i64(r1, t1);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -3058,8 +3018,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
- tcg_temp_free(t2);
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -3072,9 +3030,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32h_i64(r1, t1);
}
- tcg_temp_free(t2);
- tcg_temp_free(t1);
-
return DISAS_NEXT;
}
@@ -3098,11 +3053,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15));
tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s));
tcg_gen_mov_i64(regs[r1], t1);
- tcg_temp_free(t2);
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
- tcg_temp_free(t1);
return DISAS_NEXT;
}
@@ -3114,8 +3067,6 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
tcg_gen_add_i64(o->in2, o->in2, t1);
tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
}
- tcg_temp_free(t1);
-
return DISAS_NEXT;
}
@@ -3137,8 +3088,6 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
a2 = get_address(s, 0, get_field(s, b2), get_field(s, d2));
tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN);
tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN);
- tcg_temp_free_i64(a1);
- tcg_temp_free_i64(a2);
/* ... and indicate that we performed them while interlocked. */
gen_op_movi_cc(s, 0);
@@ -3246,8 +3195,6 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
}
tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1]));
- tcg_temp_free_i64(ar1);
-
return DISAS_NEXT;
}
@@ -3466,7 +3413,6 @@ static DisasJumpType op_maeb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
- tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@@ -3474,7 +3420,6 @@ static DisasJumpType op_madb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg(get_field(s, r3));
gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3);
- tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@@ -3482,7 +3427,6 @@ static DisasJumpType op_mseb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
- tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@@ -3490,7 +3434,6 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg(get_field(s, r3));
gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3);
- tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@@ -3501,7 +3444,6 @@ static DisasJumpType op_nabs(DisasContext *s, DisasOps *o)
tcg_gen_neg_i64(n, o->in2);
tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2);
- tcg_temp_free_i64(n);
return DISAS_NEXT;
}
@@ -3836,9 +3778,6 @@ static DisasJumpType op_rll32(DisasContext *s, DisasOps *o)
tcg_gen_extrl_i64_i32(t2, o->in2);
tcg_gen_rotl_i32(to, t1, t2);
tcg_gen_extu_i32_i64(o->out, to);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(to);
return DISAS_NEXT;
}
@@ -3993,12 +3932,10 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
h = tcg_temp_new_i64();
tcg_gen_shri_i64(h, regs[r1], 32);
tcg_gen_qemu_st32(h, a, get_mem_index(s));
- tcg_temp_free_i64(h);
break;
default:
g_assert_not_reached();
}
- tcg_temp_free_i64(a);
gen_set_label(lab);
return DISAS_NEXT;
@@ -4015,9 +3952,6 @@ static DisasJumpType op_sla(DisasContext *s, DisasOps *o)
t = o->in1;
}
gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2);
- if (s->insn->data == 31) {
- tcg_temp_free_i64(t);
- }
tcg_gen_shl_i64(o->out, o->in1, o->in2);
/* The arithmetic left shift is curious in that it does not affect
the sign bit. Copy that over from the source unchanged. */
@@ -4084,8 +4018,6 @@ static DisasJumpType op_srnmt(DisasContext *s, DisasOps *o)
tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc));
tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3);
tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc));
-
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -4126,8 +4058,6 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
/* store second operand in GR1 */
tcg_gen_mov_i64(regs[1], o->in2);
-
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -4187,9 +4117,6 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
- tcg_temp_free_i64(c1);
- tcg_temp_free_i64(c2);
- tcg_temp_free_i64(todpr);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
@@ -4403,7 +4330,6 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, psw_mask, 56);
tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
- tcg_temp_free_i64(t);
if (s->fields.op == 0xac) {
tcg_gen_andi_i64(psw_mask, psw_mask,
@@ -4514,7 +4440,6 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
}
break;
}
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -4558,8 +4483,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
tcg_gen_add_i64(o->in2, o->in2, t4);
r1 = (r1 + 1) & 15;
}
-
- tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@@ -4746,7 +4669,6 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o)
gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, pair);
- tcg_temp_free_i128(pair);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -4792,7 +4714,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
}
gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes);
- tcg_temp_free_i32(tst);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -5299,7 +5220,6 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o)
store_reg32_i64(r1 + 1, o->out);
tcg_gen_shri_i64(t, o->out, 32);
store_reg32_i64(r1, t);
- tcg_temp_free_i64(t);
}
#define SPEC_wout_r1_D32 SPEC_r1_even
@@ -6430,31 +6350,6 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
}
}
- /* Free any temporaries created by the helpers. */
- if (o.out && !o.g_out) {
- tcg_temp_free_i64(o.out);
- }
- if (o.out2 && !o.g_out2) {
- tcg_temp_free_i64(o.out2);
- }
- if (o.in1 && !o.g_in1) {
- tcg_temp_free_i64(o.in1);
- }
- if (o.in2 && !o.g_in2) {
- tcg_temp_free_i64(o.in2);
- }
- if (o.addr1) {
- tcg_temp_free_i64(o.addr1);
- }
- if (o.out_128) {
- tcg_temp_free_i128(o.out_128);
- }
- if (o.in1_128) {
- tcg_temp_free_i128(o.in1_128);
- }
- if (o.in2_128) {
- tcg_temp_free_i128(o.in2_128);
- }
/* io should be the last instruction in tb when icount is enabled */
if (unlikely(icount && ret == DISAS_NEXT)) {
ret = DISAS_TOO_MANY;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 13/91] target/s390x: Remove assert vs g_in2
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (11 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 12/91] target/s390x: Drop tcg_temp_free from translate.c Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 14/91] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext Richard Henderson
` (78 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, David Hildenbrand, Ilya Leoshkevich,
Philippe Mathieu-Daudé
These were trying to determine if o->in2 was available for
use as a temporary. It's better to just allocate a new one.
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 954a1edd10..9ad6e75434 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1428,11 +1428,11 @@ static DisasJumpType op_andi(DisasContext *s, DisasOps *o)
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
uint64_t mask = ((1ull << size) - 1) << shift;
+ TCGv_i64 t = tcg_temp_new_i64();
- assert(!o->g_in2);
- tcg_gen_shli_i64(o->in2, o->in2, shift);
- tcg_gen_ori_i64(o->in2, o->in2, ~mask);
- tcg_gen_and_i64(o->out, o->in1, o->in2);
+ tcg_gen_shli_i64(t, o->in2, shift);
+ tcg_gen_ori_i64(t, t, ~mask);
+ tcg_gen_and_i64(o->out, o->in1, t);
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
@@ -3520,10 +3520,10 @@ static DisasJumpType op_ori(DisasContext *s, DisasOps *o)
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
uint64_t mask = ((1ull << size) - 1) << shift;
+ TCGv_i64 t = tcg_temp_new_i64();
- assert(!o->g_in2);
- tcg_gen_shli_i64(o->in2, o->in2, shift);
- tcg_gen_or_i64(o->out, o->in1, o->in2);
+ tcg_gen_shli_i64(t, o->in2, shift);
+ tcg_gen_or_i64(o->out, o->in1, t);
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
@@ -4832,10 +4832,10 @@ static DisasJumpType op_xori(DisasContext *s, DisasOps *o)
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
uint64_t mask = ((1ull << size) - 1) << shift;
+ TCGv_i64 t = tcg_temp_new_i64();
- assert(!o->g_in2);
- tcg_gen_shli_i64(o->in2, o->in2, shift);
- tcg_gen_xor_i64(o->out, o->in1, o->in2);
+ tcg_gen_shli_i64(t, o->in2, shift);
+ tcg_gen_xor_i64(o->out, o->in1, t);
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 14/91] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (12 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 13/91] target/s390x: Remove assert vs g_in2 Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 15/91] tcg: Create tcg/tcg-temp-internal.h Richard Henderson
` (77 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, David Hildenbrand, Ilya Leoshkevich,
Philippe Mathieu-Daudé
These fields are no longer read, so remove them and the writes.
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 9ad6e75434..7969051ce9 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1061,7 +1061,6 @@ static const DisasFormatInfo format_info[] = {
them, and store them back. See the "in1", "in2", "prep", "wout" sets
of routines below for more details. */
typedef struct {
- bool g_out, g_out2, g_in1, g_in2;
TCGv_i64 out, out2, in1, in2;
TCGv_i64 addr1;
TCGv_i128 out_128, in1_128, in2_128;
@@ -3159,9 +3158,7 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o)
static DisasJumpType op_mov2(DisasContext *s, DisasOps *o)
{
o->out = o->in2;
- o->g_out = o->g_in2;
o->in2 = NULL;
- o->g_in2 = false;
return DISAS_NEXT;
}
@@ -3171,9 +3168,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
TCGv ar1 = tcg_temp_new_i64();
o->out = o->in2;
- o->g_out = o->g_in2;
o->in2 = NULL;
- o->g_in2 = false;
switch (s->base.tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
@@ -3202,11 +3197,8 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o)
{
o->out = o->in1;
o->out2 = o->in2;
- o->g_out = o->g_in1;
- o->g_out2 = o->g_in2;
o->in1 = NULL;
o->in2 = NULL;
- o->g_in1 = o->g_in2 = false;
return DISAS_NEXT;
}
@@ -3708,7 +3700,6 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
/* If this is a test-only form, arrange to discard the result. */
if (i3 & 0x80) {
o->out = tcg_temp_new_i64();
- o->g_out = false;
}
i3 &= 63;
@@ -4874,7 +4865,6 @@ static DisasJumpType op_zero2(DisasContext *s, DisasOps *o)
{
o->out = tcg_const_i64(0);
o->out2 = o->out;
- o->g_out2 = true;
return DISAS_NEXT;
}
@@ -5142,7 +5132,6 @@ static void prep_new_x(DisasContext *s, DisasOps *o)
static void prep_r1(DisasContext *s, DisasOps *o)
{
o->out = regs[get_field(s, r1)];
- o->g_out = true;
}
#define SPEC_prep_r1 0
@@ -5151,7 +5140,6 @@ static void prep_r1_P(DisasContext *s, DisasOps *o)
int r1 = get_field(s, r1);
o->out = regs[r1];
o->out2 = regs[r1 + 1];
- o->g_out = o->g_out2 = true;
}
#define SPEC_prep_r1_P SPEC_r1_even
@@ -5375,7 +5363,6 @@ static void in1_r1(DisasContext *s, DisasOps *o)
static void in1_r1_o(DisasContext *s, DisasOps *o)
{
o->in1 = regs[get_field(s, r1)];
- o->g_in1 = true;
}
#define SPEC_in1_r1_o 0
@@ -5409,7 +5396,6 @@ static void in1_r1p1(DisasContext *s, DisasOps *o)
static void in1_r1p1_o(DisasContext *s, DisasOps *o)
{
o->in1 = regs[get_field(s, r1) + 1];
- o->g_in1 = true;
}
#define SPEC_in1_r1p1_o SPEC_r1_even
@@ -5464,7 +5450,6 @@ static void in1_r3(DisasContext *s, DisasOps *o)
static void in1_r3_o(DisasContext *s, DisasOps *o)
{
o->in1 = regs[get_field(s, r3)];
- o->g_in1 = true;
}
#define SPEC_in1_r3_o 0
@@ -5595,7 +5580,6 @@ static void in1_m1_64(DisasContext *s, DisasOps *o)
static void in2_r1_o(DisasContext *s, DisasOps *o)
{
o->in2 = regs[get_field(s, r1)];
- o->g_in2 = true;
}
#define SPEC_in2_r1_o 0
@@ -5630,7 +5614,6 @@ static void in2_r2(DisasContext *s, DisasOps *o)
static void in2_r2_o(DisasContext *s, DisasOps *o)
{
o->in2 = regs[get_field(s, r2)];
- o->g_in2 = true;
}
#define SPEC_in2_r2_o 0
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 15/91] tcg: Create tcg/tcg-temp-internal.h
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (13 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 14/91] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 16/91] include/exec: Set default `NB_MMU_MODES` to 16 Richard Henderson
` (76 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé
Move the tcg_temp_free_* and tcg_temp_ebb_new_* declarations
and inlines to the new header. These are private to the
implementation, and will prevent tcg_temp_free_* from creeping
back into the guest front ends.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-temp-internal.h | 83 +++++++++++++++++++++++++++++++++
include/tcg/tcg.h | 54 ---------------------
accel/tcg/plugin-gen.c | 1 +
tcg/tcg-op-gvec.c | 1 +
tcg/tcg-op-vec.c | 1 +
tcg/tcg-op.c | 1 +
tcg/tcg.c | 1 +
7 files changed, 88 insertions(+), 54 deletions(-)
create mode 100644 include/tcg/tcg-temp-internal.h
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
new file mode 100644
index 0000000000..dded2917e5
--- /dev/null
+++ b/include/tcg/tcg-temp-internal.h
@@ -0,0 +1,83 @@
+/*
+ * TCG internals related to TCG temp allocation
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TCG_TEMP_INTERNAL_H
+#define TCG_TEMP_INTERNAL_H
+
+/*
+ * Allocation and freeing of EBB temps is reserved to TCG internals
+ */
+
+void tcg_temp_free_internal(TCGTemp *);
+
+static inline void tcg_temp_free_i32(TCGv_i32 arg)
+{
+ tcg_temp_free_internal(tcgv_i32_temp(arg));
+}
+
+static inline void tcg_temp_free_i64(TCGv_i64 arg)
+{
+ tcg_temp_free_internal(tcgv_i64_temp(arg));
+}
+
+static inline void tcg_temp_free_i128(TCGv_i128 arg)
+{
+ tcg_temp_free_internal(tcgv_i128_temp(arg));
+}
+
+static inline void tcg_temp_free_ptr(TCGv_ptr arg)
+{
+ tcg_temp_free_internal(tcgv_ptr_temp(arg));
+}
+
+static inline void tcg_temp_free_vec(TCGv_vec arg)
+{
+ tcg_temp_free_internal(tcgv_vec_temp(arg));
+}
+
+static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
+ return temp_tcgv_i32(t);
+}
+
+static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
+ return temp_tcgv_i64(t);
+}
+
+static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
+ return temp_tcgv_i128(t);
+}
+
+static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
+ return temp_tcgv_ptr(t);
+}
+
+#endif /* TCG_TEMP_FREE_H */
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index a5cf21be83..00c4fbe613 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -862,35 +862,9 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
intptr_t, const char *);
TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind);
-void tcg_temp_free_internal(TCGTemp *);
TCGv_vec tcg_temp_new_vec(TCGType type);
TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
-static inline void tcg_temp_free_i32(TCGv_i32 arg)
-{
- tcg_temp_free_internal(tcgv_i32_temp(arg));
-}
-
-static inline void tcg_temp_free_i64(TCGv_i64 arg)
-{
- tcg_temp_free_internal(tcgv_i64_temp(arg));
-}
-
-static inline void tcg_temp_free_i128(TCGv_i128 arg)
-{
- tcg_temp_free_internal(tcgv_i128_temp(arg));
-}
-
-static inline void tcg_temp_free_ptr(TCGv_ptr arg)
-{
- tcg_temp_free_internal(tcgv_ptr_temp(arg));
-}
-
-static inline void tcg_temp_free_vec(TCGv_vec arg)
-{
- tcg_temp_free_internal(tcgv_vec_temp(arg));
-}
-
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
{
@@ -898,13 +872,6 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i32(t);
}
-/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
-static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
- return temp_tcgv_i32(t);
-}
-
static inline TCGv_i32 tcg_temp_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB);
@@ -918,26 +885,12 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i64(t);
}
-/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
-static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
- return temp_tcgv_i64(t);
-}
-
static inline TCGv_i64 tcg_temp_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB);
return temp_tcgv_i64(t);
}
-/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
-static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
- return temp_tcgv_i128(t);
-}
-
static inline TCGv_i128 tcg_temp_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB);
@@ -951,13 +904,6 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_ptr(t);
}
-/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
-static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
- return temp_tcgv_ptr(t);
-}
-
static inline TCGv_ptr tcg_temp_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB);
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index c42a436c0c..5efb8db258 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -44,6 +44,7 @@
*/
#include "qemu/osdep.h"
#include "tcg/tcg.h"
+#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "exec/exec-all.h"
#include "exec/plugin-gen.h"
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 291a65c4bf..047a832f44 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
+#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "tcg/tcg-gvec-desc.h"
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 966d41d65a..0f023f42c6 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
+#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-mo.h"
#include "tcg-internal.h"
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 77658a88f0..1a039a292c 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
+#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-mo.h"
#include "exec/plugin-gen.h"
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e4fccbd0d8..d2993826c8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -60,6 +60,7 @@
#include "elf.h"
#include "exec/log.h"
#include "tcg/tcg-ldst.h"
+#include "tcg/tcg-temp-internal.h"
#include "tcg-internal.h"
#include "accel/tcg/perf.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 16/91] include/exec: Set default `NB_MMU_MODES` to 16
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (14 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 15/91] tcg: Create tcg/tcg-temp-internal.h Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 17/91] target/alpha: Remove `NB_MMU_MODES` define Richard Henderson
` (75 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-2-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index be920d4208..7d9e1f50d8 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -36,9 +36,6 @@
#ifndef TARGET_LONG_BITS
# error TARGET_LONG_BITS must be defined in cpu-param.h
#endif
-#ifndef NB_MMU_MODES
-# error NB_MMU_MODES must be defined in cpu-param.h
-#endif
#ifndef TARGET_PHYS_ADDR_SPACE_BITS
# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
#endif
@@ -55,6 +52,14 @@
# endif
#endif
+/*
+ * Fix the number of mmu modes to 16, which is also the maximum
+ * supported by the softmmu tlb api.
+ */
+#ifndef NB_MMU_MODES
+#define NB_MMU_MODES 16
+#endif
+
#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
/* target_ulong is the type of a virtual address */
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 17/91] target/alpha: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (15 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 16/91] include/exec: Set default `NB_MMU_MODES` to 16 Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 18/91] target/arm: " Richard Henderson
` (74 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-3-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu-param.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index 17cd14e590..68c46f7998 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -15,6 +15,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 44
#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
-#define NB_MMU_MODES 3
-
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 18/91] target/arm: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (16 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 17/91] target/alpha: Remove `NB_MMU_MODES` define Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 19/91] target/avr: " Richard Henderson
` (73 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-4-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-param.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index b7bde18986..b3b35f7aa1 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -45,6 +45,4 @@
bool guarded;
#endif
-#define NB_MMU_MODES 12
-
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 19/91] target/avr: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (17 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 18/91] target/arm: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 20/91] target/cris: " Richard Henderson
` (72 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-5-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 7ef4e7c679..9a92bc74fc 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -31,6 +31,5 @@
#define TARGET_PAGE_BITS 8
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
-#define NB_MMU_MODES 2
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 20/91] target/cris: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (18 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 19/91] target/avr: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 21/91] target/hexagon: " Richard Henderson
` (71 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-6-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h
index 12ec22d8df..b31b742c0d 100644
--- a/target/cris/cpu-param.h
+++ b/target/cris/cpu-param.h
@@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define NB_MMU_MODES 2
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 21/91] target/hexagon: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (19 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 20/91] target/cris: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 22/91] target/hppa: " Richard Henderson
` (70 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-7-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/cpu-param.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index e8ed5468d9..71b4a9b83e 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -24,6 +24,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define NB_MMU_MODES 1
-
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 22/91] target/hppa: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (20 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 21/91] target/hexagon: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 23/91] target/i386: " Richard Henderson
` (69 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-8-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index a48a2701ae..c2791ae5f2 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -29,6 +29,5 @@
# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
-#define NB_MMU_MODES 5
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 23/91] target/i386: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (21 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 22/91] target/hppa: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 24/91] target/loongarch: " Richard Henderson
` (68 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-9-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index abad52af20..911b4cd51b 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -23,6 +23,5 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
-#define NB_MMU_MODES 5
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 24/91] target/loongarch: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (22 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 23/91] target/i386: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 25/91] target/m68k: " Richard Henderson
` (67 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-10-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 414d8fff46..1265dc7cb5 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -13,6 +13,5 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 48
#define TARGET_PAGE_BITS 14
-#define NB_MMU_MODES 5
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 25/91] target/m68k: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (23 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 24/91] target/loongarch: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 26/91] target/microblaze: " Richard Henderson
` (66 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-11-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 44a8d193f0..39dcbcece8 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -17,6 +17,5 @@
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define NB_MMU_MODES 2
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 26/91] target/microblaze: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (24 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 25/91] target/m68k: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 27/91] target/mips: " Richard Henderson
` (65 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-12-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu-param.h | 1 -
target/microblaze/cpu.h | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 5e54ea0108..9770b0eb52 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -28,6 +28,5 @@
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
-#define NB_MMU_MODES 3
#endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index f66df02226..88324d0bc1 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -394,7 +394,7 @@ void mb_tcg_init(void);
#define MMU_NOMMU_IDX 0
#define MMU_KERNEL_IDX 1
#define MMU_USER_IDX 2
-/* See NB_MMU_MODES further up the file. */
+/* See NB_MMU_MODES in cpu-defs.h. */
#include "exec/cpu-all.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 27/91] target/mips: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (25 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 26/91] target/microblaze: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 28/91] target/nios2: " Richard Henderson
` (64 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-13-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index f4c76994ea..594c91a156 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -29,6 +29,5 @@
#define TARGET_PAGE_BITS_VARY
#define TARGET_PAGE_BITS_MIN 12
#endif
-#define NB_MMU_MODES 4
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 28/91] target/nios2: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (26 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 27/91] target/mips: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 29/91] target/openrisc: " Richard Henderson
` (63 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-14-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h
index 177d720864..767bba4b7b 100644
--- a/target/nios2/cpu-param.h
+++ b/target/nios2/cpu-param.h
@@ -16,6 +16,5 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-#define NB_MMU_MODES 2
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 29/91] target/openrisc: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (27 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 28/91] target/nios2: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 30/91] target/ppc: " Richard Henderson
` (62 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-15-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 73be699f36..3f08207485 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define NB_MMU_MODES 3
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 30/91] target/ppc: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (28 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 29/91] target/openrisc: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 31/91] target/riscv: " Richard Henderson
` (61 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-16-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index ea377b7d06..0a0416e0a8 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -32,6 +32,5 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
-#define NB_MMU_MODES 10
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 31/91] target/riscv: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (29 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 30/91] target/ppc: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 32/91] target/rx: " Richard Henderson
` (60 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-17-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index ebaf26d26d..b2a9396dec 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -27,6 +27,5 @@
* - S mode HLV/HLVX/HSV 0b101
* - M mode HLV/HLVX/HSV 0b111
*/
-#define NB_MMU_MODES 8
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 32/91] target/rx: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (30 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 31/91] target/riscv: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 33/91] target/s390x: " Richard Henderson
` (59 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-18-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/cpu-param.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index b156ad1ca0..521d669bdf 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -25,6 +25,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define NB_MMU_MODES 1
-
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 33/91] target/s390x: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (31 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 32/91] target/rx: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 34/91] target/sh4: " Richard Henderson
` (58 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-19-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index bf951a002e..84ca08626b 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
-#define NB_MMU_MODES 4
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 34/91] target/sh4: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (32 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 33/91] target/s390x: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 35/91] target/sparc: " Richard Henderson
` (57 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-20-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 98a02509bb..a7cdb7edb6 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,6 +16,5 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-#define NB_MMU_MODES 2
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 35/91] target/sparc: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (33 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 34/91] target/sh4: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 36/91] target/tricore: " Richard Henderson
` (56 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-21-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/cpu-param.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 72ddc4a34f..cb11980404 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -16,13 +16,11 @@
# else
# define TARGET_VIRT_ADDR_SPACE_BITS 44
# endif
-# define NB_MMU_MODES 6
#else
# define TARGET_LONG_BITS 32
# define TARGET_PAGE_BITS 12 /* 4k */
# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
-# define NB_MMU_MODES 3
#endif
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 36/91] target/tricore: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (34 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 35/91] target/sparc: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 37/91] target/xtensa: " Richard Henderson
` (55 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-22-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index 2727913047..e29d551dd6 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 14
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define NB_MMU_MODES 3
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 37/91] target/xtensa: Remove `NB_MMU_MODES` define
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (35 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 36/91] target/tricore: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 38/91] include/exec: Remove guards around `NB_MMU_MODES` Richard Henderson
` (54 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-23-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index b53e9a3e08..b1da0555de 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -16,6 +16,5 @@
#else
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-#define NB_MMU_MODES 4
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 38/91] include/exec: Remove guards around `NB_MMU_MODES`
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (36 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 37/91] target/xtensa: " Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
` (53 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Johansson, Philippe Mathieu-Daudé,
Alex Bennée
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-24-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 7d9e1f50d8..e230bb59f5 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -56,9 +56,7 @@
* Fix the number of mmu modes to 16, which is also the maximum
* supported by the softmmu tlb api.
*/
-#ifndef NB_MMU_MODES
#define NB_MMU_MODES 16
-#endif
#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (37 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 38/91] include/exec: Remove guards around `NB_MMU_MODES` Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:04 ` [PULL v2 40/91] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
` (52 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
The use of separate data/port variables is existing
practice elsewhere, e.g. SBI, CBI.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/translate.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index b9506a8d86..190d0c3f97 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -1288,12 +1288,13 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
*/
static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
{
- TCGv temp = tcg_const_i32(a->reg);
+ TCGv data = tcg_temp_new_i32();
+ TCGv port = tcg_constant_i32(a->reg);
- gen_helper_inb(temp, cpu_env, temp);
- tcg_gen_andi_tl(temp, temp, 1 << a->bit);
+ gen_helper_inb(data, cpu_env, port);
+ tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
- ctx->skip_var0 = temp;
+ ctx->skip_var0 = data;
return true;
}
@@ -1305,12 +1306,13 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
*/
static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
{
- TCGv temp = tcg_const_i32(a->reg);
+ TCGv data = tcg_temp_new_i32();
+ TCGv port = tcg_constant_i32(a->reg);
- gen_helper_inb(temp, cpu_env, temp);
- tcg_gen_andi_tl(temp, temp, 1 << a->bit);
+ gen_helper_inb(data, cpu_env, port);
+ tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
- ctx->skip_var0 = temp;
+ ctx->skip_var0 = data;
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 40/91] target/avr: Avoid use of tcg_const_i32 throughout
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (38 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
@ 2023-03-09 20:04 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 41/91] target/cris: " Richard Henderson
` (51 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/translate.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 190d0c3f97..a6aeae6dfa 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -400,7 +400,7 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a)
static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv Rr = tcg_const_i32(a->imm);
+ TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */
@@ -425,7 +425,7 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -453,9 +453,9 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv Rr = tcg_const_i32(a->imm);
+ TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -637,7 +637,7 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a)
static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv t0 = tcg_const_i32(0);
+ TCGv t0 = tcg_constant_i32(0);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
@@ -930,19 +930,19 @@ static void gen_jmp_z(DisasContext *ctx)
static void gen_push_ret(DisasContext *ctx, int ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
- TCGv t0 = tcg_const_i32((ret & 0x0000ff));
+ TCGv t0 = tcg_constant_i32(ret & 0x0000ff);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
- TCGv t0 = tcg_const_i32((ret & 0x00ffff));
+ TCGv t0 = tcg_constant_i32(ret & 0x00ffff);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
- TCGv lo = tcg_const_i32((ret & 0x0000ff));
- TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
+ TCGv lo = tcg_constant_i32(ret & 0x0000ff);
+ TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8);
tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
@@ -1211,7 +1211,7 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@@ -1238,7 +1238,7 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
{
TCGv Rd = cpu_r[a->rd];
int Imm = a->imm;
- TCGv Rr = tcg_const_i32(Imm);
+ TCGv Rr = tcg_constant_i32(Imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
@@ -2124,7 +2124,7 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
static bool trans_IN(DisasContext *ctx, arg_IN *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv port = tcg_const_i32(a->imm);
+ TCGv port = tcg_constant_i32(a->imm);
gen_helper_inb(Rd, cpu_env, port);
return true;
@@ -2137,7 +2137,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
{
TCGv Rd = cpu_r[a->rd];
- TCGv port = tcg_const_i32(a->imm);
+ TCGv port = tcg_constant_i32(a->imm);
gen_helper_outb(cpu_env, port, Rd);
return true;
@@ -2405,7 +2405,7 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
{
TCGv data = tcg_temp_new_i32();
- TCGv port = tcg_const_i32(a->reg);
+ TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
@@ -2420,7 +2420,7 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
{
TCGv data = tcg_temp_new_i32();
- TCGv port = tcg_const_i32(a->reg);
+ TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 41/91] target/cris: Avoid use of tcg_const_i32 throughout
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (39 preceding siblings ...)
2023-03-09 20:04 ` [PULL v2 40/91] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
` (50 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/translate.c | 46 +++++++++++++++------------------
target/cris/translate_v10.c.inc | 26 +++++++++----------
2 files changed, 34 insertions(+), 38 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 5172c9b9b2..b2beb9964d 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -175,10 +175,7 @@ static const int preg_sizes[] = {
#define t_gen_mov_env_TN(member, tn) \
tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \
- do { \
- TCGv tc = tcg_const_tl(c); \
- t_gen_mov_env_TN(member, tc); \
- } while (0)
+ t_gen_mov_env_TN(member, tcg_constant_tl(c))
static inline void t_gen_mov_TN_preg(TCGv tn, int r)
{
@@ -268,8 +265,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index)
{
- TCGv_i32 tmp = tcg_const_i32(index);
- gen_helper_raise_exception(cpu_env, tmp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
}
static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
@@ -277,7 +273,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
TCGv t0, t_31;
t0 = tcg_temp_new();
- t_31 = tcg_const_tl(31);
+ t_31 = tcg_constant_tl(31);
tcg_gen_shl_tl(d, a, b);
tcg_gen_sub_tl(t0, t_31, b);
@@ -1250,7 +1246,7 @@ static int dec_addq(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(dc->op1);
+ c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_ADD,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1274,7 +1270,7 @@ static int dec_subq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(dc->op1);
+ c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_SUB,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1289,7 +1285,7 @@ static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1304,7 +1300,7 @@ static int dec_andq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_AND,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1318,7 +1314,7 @@ static int dec_orq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_OR,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@@ -1330,7 +1326,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
- c = tcg_const_tl(dc->op1);
+ c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]);
@@ -1945,8 +1941,8 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
- c1 = tcg_const_tl(dc->op1);
- c2 = tcg_const_tl(dc->op2);
+ c1 = tcg_constant_tl(dc->op1);
+ c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(cpu_env, c2, c1);
return 2;
@@ -1955,8 +1951,8 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
- c1 = tcg_const_tl(dc->op1);
- c2 = tcg_const_tl(dc->op2);
+ c1 = tcg_constant_tl(dc->op1);
+ c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(cpu_env, c1, c2);
return 2;
@@ -2237,7 +2233,7 @@ static int dec_test_m(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
- c = tcg_const_tl(0);
+ c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], t[1], c, memsize_zz(dc));
do_postinc(dc, memsize);
@@ -2582,7 +2578,7 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
if (dc->op2 > 15) {
abort();
}
- c = tcg_const_tl(dc->pc + 4);
+ c = tcg_constant_tl(dc->pc + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
@@ -2598,7 +2594,7 @@ static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
- c = tcg_const_tl(dc->pc + 8);
+ c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2616,7 +2612,7 @@ static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
- c = tcg_const_tl(dc->pc + 8 + 4);
+ c = tcg_constant_tl(dc->pc + 8 + 4);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2632,7 +2628,7 @@ static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
- c = tcg_const_tl(dc->pc + 4 + 4);
+ c = tcg_constant_tl(dc->pc + 4 + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
return 2;
@@ -2664,7 +2660,7 @@ static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
- c = tcg_const_tl(dc->pc + 8);
+ c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2681,7 +2677,7 @@ static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
- c = tcg_const_tl(dc->pc + 12);
+ c = tcg_constant_tl(dc->pc + 12);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@@ -2695,7 +2691,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
if (dc->op2 == 15) {
- tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);
diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc
index b03b2ef746..32338bb69b 100644
--- a/target/cris/translate_v10.c.inc
+++ b/target/cris/translate_v10.c.inc
@@ -251,7 +251,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(simm);
+ c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -259,7 +259,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(simm);
+ c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -267,7 +267,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -275,7 +275,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(simm);
+ c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -285,7 +285,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
op = imm & (1 << 5);
imm &= 0x1f;
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
if (op) {
cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
@@ -305,7 +305,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
}
imm &= 0x1f;
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
cris_alu(dc, op, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -313,7 +313,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(imm);
+ c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -321,7 +321,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- c = tcg_const_tl(simm);
+ c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@@ -1014,7 +1014,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
cris_alu_m_alloc_temps(t);
insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
- c = tcg_const_tl(0);
+ c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
t[0], c, size);
break;
@@ -1111,7 +1111,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
if (dc->mode == CRISV10_MODE_AUTOINC)
insn_len += size;
- c = tcg_const_tl(dc->pc + insn_len);
+ c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
dc->jmp_pc = imm;
cris_prepare_jmp(dc, JMP_DIRECT);
@@ -1121,7 +1121,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("break %d\n", dc->src);
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc + 2);
- c = tcg_const_tl(dc->src + 2);
+ c = tcg_constant_tl(dc->src + 2);
t_gen_mov_env_TN(trap_vector, c);
t_gen_raise_exception(EXCP_BREAK);
dc->base.is_jmp = DISAS_NORETURN;
@@ -1130,7 +1130,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
dc->opcode, dc->src, dc->dst);
t[0] = tcg_temp_new();
- c = tcg_const_tl(dc->pc + insn_len);
+ c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
crisv10_prepare_memaddr(dc, t[0], size);
gen_load(dc, env_btarget, t[0], 4, 0);
@@ -1153,7 +1153,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
dc->pc, dc->opcode, dc->dst, dc->src);
tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
- c = tcg_const_tl(dc->pc + insn_len);
+ c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (40 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 41/91] target/cris: " Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 43/91] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
` (49 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Use a C test instead of a pre-processor test for the id.
Use tcg_constant_i64 instead of tcg_const_i64.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index cb4fd1fd62..3ea50d0cec 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3547,12 +3547,16 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
{
+ uint64_t ret;
+
+ if (TARGET_REGISTER_BITS == 64) {
+ ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */
+ } else {
+ ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */
+ }
+
nullify_over(ctx);
-#if TARGET_REGISTER_BITS == 64
- save_frd(0, tcg_const_i64(0x13080000000000ULL)); /* PA8700 (PCX-W2) */
-#else
- save_frd(0, tcg_const_i64(0x0f080000000000ULL)); /* PA7300LC (PCX-L2) */
-#endif
+ save_frd(0, tcg_constant_i64(ret));
return nullify_end(ctx);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 43/91] target/hppa: Avoid use of tcg_const_i32 throughout
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (41 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 44/91] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
` (48 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All uses were read-write, so replace with a new
allocation and initialization.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 3ea50d0cec..6a3154ebc6 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -135,8 +135,6 @@
#define tcg_gen_extract_reg tcg_gen_extract_i64
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
#define tcg_gen_extract2_reg tcg_gen_extract2_i64
-#define tcg_const_reg tcg_const_i64
-#define tcg_const_local_reg tcg_const_local_i64
#define tcg_constant_reg tcg_constant_i64
#define tcg_gen_movcond_reg tcg_gen_movcond_i64
#define tcg_gen_add2_reg tcg_gen_add2_i64
@@ -228,8 +226,6 @@
#define tcg_gen_extract_reg tcg_gen_extract_i32
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
#define tcg_gen_extract2_reg tcg_gen_extract2_i32
-#define tcg_const_reg tcg_const_i32
-#define tcg_const_local_reg tcg_const_local_i32
#define tcg_constant_reg tcg_constant_i32
#define tcg_gen_movcond_reg tcg_gen_movcond_i32
#define tcg_gen_add2_reg tcg_gen_add2_i32
@@ -574,7 +570,9 @@ static TCGv_i32 load_frw_i32(unsigned rt)
static TCGv_i32 load_frw0_i32(unsigned rt)
{
if (rt == 0) {
- return tcg_const_i32(0);
+ TCGv_i32 ret = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ret, 0);
+ return ret;
} else {
return load_frw_i32(rt);
}
@@ -582,15 +580,15 @@ static TCGv_i32 load_frw0_i32(unsigned rt)
static TCGv_i64 load_frw0_i64(unsigned rt)
{
+ TCGv_i64 ret = tcg_temp_new_i64();
if (rt == 0) {
- return tcg_const_i64(0);
+ tcg_gen_movi_i64(ret, 0);
} else {
- TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_ld32u_i64(ret, cpu_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
- return ret;
}
+ return ret;
}
static void save_frw_i32(unsigned rt, TCGv_i32 val)
@@ -613,7 +611,9 @@ static TCGv_i64 load_frd(unsigned rt)
static TCGv_i64 load_frd0(unsigned rt)
{
if (rt == 0) {
- return tcg_const_i64(0);
+ TCGv_i64 ret = tcg_temp_new_i64();
+ tcg_gen_movi_i64(ret, 0);
+ return ret;
} else {
return load_frd(rt);
}
@@ -3330,7 +3330,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Convert big-endian bit numbering in SAR to left-shift. */
tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1);
- mask = tcg_const_reg(msb + (msb - 1));
+ mask = tcg_temp_new();
+ tcg_gen_movi_reg(mask, msb + (msb - 1));
tcg_gen_and_reg(tmp, val, mask);
if (rs) {
tcg_gen_shl_reg(mask, mask, shift);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 44/91] target/i386: Avoid use of tcg_const_* throughout
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (42 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 43/91] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 45/91] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
` (47 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All uses are strictly read-only. Most of the obviously so,
as direct arguments to gen_helper_*.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 83 +++++++++++++++++++------------------
1 file changed, 42 insertions(+), 41 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index fa422ebd0b..9dfad2f7bc 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -884,7 +884,7 @@ static void gen_compute_eflags(DisasContext *s)
live = cc_op_live[s->cc_op] & ~USES_CC_SRCT;
dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2);
if (dead) {
- zero = tcg_const_tl(0);
+ zero = tcg_constant_tl(0);
if (dead & USES_CC_DST) {
dst = zero;
}
@@ -1412,7 +1412,7 @@ static void gen_helper_fp_arith_ST0_FT0(int op)
/* NOTE the exception in "r" op ordering */
static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
{
- TCGv_i32 tmp = tcg_const_i32(opreg);
+ TCGv_i32 tmp = tcg_constant_i32(opreg);
switch (op) {
case 0:
gen_helper_fadd_STN_ST0(cpu_env, tmp);
@@ -1439,7 +1439,7 @@ static void gen_exception(DisasContext *s, int trapno)
{
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno));
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1633,7 +1633,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
/* Store the results into the CC variables. If we know that the
variable must be dead, store unconditionally. Otherwise we'll
need to not disrupt the current contents. */
- z_tl = tcg_const_tl(0);
+ z_tl = tcg_constant_tl(0);
if (cc_op_live[s->cc_op] & USES_CC_DST) {
tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl,
result, cpu_cc_dst);
@@ -1657,7 +1657,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
}
/* Conditionally store the CC_OP value. */
- z32 = tcg_const_i32(0);
+ z32 = tcg_constant_i32(0);
s32 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(s32, count);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop);
@@ -1813,7 +1813,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
exactly as we computed above. */
- t0 = tcg_const_i32(0);
+ t0 = tcg_constant_i32(0);
t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, s->T1);
tcg_gen_movi_i32(s->tmp2_i32, CC_OP_ADCOX);
@@ -2497,7 +2497,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
cc.reg = t0;
}
if (!cc.use_reg2) {
- cc.reg2 = tcg_const_tl(cc.imm);
+ cc.reg2 = tcg_constant_tl(cc.imm);
}
tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2,
@@ -2525,7 +2525,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg)
{
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32);
+ gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i32);
/* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always
stop as a special handling must be done to disable hardware
@@ -4344,7 +4344,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_v_reg(s, ot, s->T1, reg);
if (shift) {
- TCGv imm = tcg_const_tl(x86_ldub_code(env, s));
+ TCGv imm = tcg_constant_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm);
} else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
@@ -4503,7 +4503,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x0c: /* fldenv mem */
gen_helper_fldenv(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0d: /* fldcw mem */
@@ -4514,7 +4514,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x0e: /* fnstenv mem */
gen_helper_fstenv(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0f: /* fnstcw mem */
@@ -4532,12 +4532,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x2c: /* frstor mem */
gen_helper_frstor(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2e: /* fnsave mem */
gen_helper_fsave(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2f: /* fnstsw mem */
@@ -4587,12 +4587,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
case 0x08: /* fld sti */
gen_helper_fpush(cpu_env);
gen_helper_fmov_ST0_STN(cpu_env,
- tcg_const_i32((opreg + 1) & 7));
+ tcg_constant_i32((opreg + 1) & 7));
break;
case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */
- gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opreg));
break;
case 0x0a: /* grp d9/2 */
switch (rm) {
@@ -4732,27 +4732,27 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
} else {
gen_helper_fmov_FT0_STN(cpu_env,
- tcg_const_i32(opreg));
+ tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1);
}
}
break;
case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env);
break;
case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
break;
case 0x15: /* da/5 */
switch (rm) {
case 1: /* fucompp */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env);
@@ -4786,7 +4786,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
@@ -4795,36 +4795,36 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x28: /* ffree sti */
- gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
break;
case 0x2a: /* fst sti */
- gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
break;
case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */
- gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env);
break;
case 0x2c: /* fucom st(i) */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env);
break;
case 0x2d: /* fucomp st(i) */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
break;
case 0x33: /* de/3 */
switch (rm) {
case 1: /* fcompp */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env);
@@ -4834,7 +4834,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
break;
case 0x38: /* ffreep sti, undocumented op */
- gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env);
break;
case 0x3c: /* df/4 */
@@ -4853,7 +4853,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
@@ -4863,7 +4863,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
@@ -4886,7 +4886,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1);
- gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_ST0_STN(cpu_env,
+ tcg_constant_i32(opreg));
gen_set_label(l1);
}
break;
@@ -5092,8 +5093,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
- tcg_const_i32(val));
+ gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1),
+ tcg_constant_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
@@ -5120,7 +5121,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!check_vm86_iopl(s)) {
break;
}
- gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
+ gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1));
} else {
gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s));
@@ -5509,7 +5510,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (val == 0) {
gen_exception(s, EXCP00_DIVZ);
} else {
- gen_helper_aam(cpu_env, tcg_const_i32(val));
+ gen_helper_aam(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
}
break;
@@ -5517,7 +5518,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
- gen_helper_aad(cpu_env, tcg_const_i32(val));
+ gen_helper_aad(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
break;
/************************/
@@ -5698,7 +5699,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) {
gen_exception_gpf(s);
} else {
- gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
+ gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
@@ -5717,7 +5718,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) {
gen_exception_gpf(s);
} else {
- gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
+ gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS);
@@ -5923,7 +5924,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),
+ gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN;
@@ -5947,7 +5948,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1));
+ gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdb: /* VMSAVE */
@@ -5959,7 +5960,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1));
+ gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdc: /* STGI */
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 45/91] target/m68k: Avoid tcg_const_i32 when modified
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (43 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 44/91] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
` (46 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
In several instances, a temp is initialized with a
for use as a constant, and then subsequently used
as an unrelated temp. Split them.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 29 ++++++++++++++++-------------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 3055d2d246..0002d80bf9 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1631,8 +1631,8 @@ static void bcd_add(TCGv dest, TCGv src)
* = result with some possible exceeding 0x6
*/
- t0 = tcg_const_i32(0x066);
- tcg_gen_add_i32(t0, t0, src);
+ t0 = tcg_temp_new();
+ tcg_gen_addi_i32(t0, src, 0x066);
t1 = tcg_temp_new();
tcg_gen_add_i32(t1, t0, dest);
@@ -1818,7 +1818,8 @@ DISAS_INSN(nbcd)
SRC_EA(env, src, OS_BYTE, 0, &addr);
- dest = tcg_const_i32(0);
+ dest = tcg_temp_new();
+ tcg_gen_movi_i32(dest, 0);
bcd_sub(dest, src);
DEST_EA(env, insn, OS_BYTE, dest, &addr);
@@ -1896,8 +1897,8 @@ DISAS_INSN(bitop_reg)
else
tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
- tmp = tcg_const_i32(1);
- tcg_gen_shl_i32(tmp, tmp, src2);
+ tmp = tcg_temp_new();
+ tcg_gen_shl_i32(tmp, tcg_constant_i32(1), src2);
tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
@@ -3076,7 +3077,7 @@ DISAS_INSN(suba)
static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
{
- TCGv tmp;
+ TCGv tmp, zero;
gen_flush_flags(s); /* compute old Z */
@@ -3085,14 +3086,15 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
* (X, N) = dest - (src + X);
*/
- tmp = tcg_const_i32(0);
- tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
- tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
+ zero = tcg_constant_i32(0);
+ tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, zero, QREG_CC_X, zero);
+ tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, zero, QREG_CC_N, QREG_CC_X);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
/* Compute signed-overflow for subtract. */
+ tmp = tcg_temp_new();
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
tcg_gen_xor_i32(tmp, dest, src);
tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
@@ -3279,7 +3281,7 @@ DISAS_INSN(adda)
static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
{
- TCGv tmp;
+ TCGv tmp, zero;
gen_flush_flags(s); /* compute old Z */
@@ -3288,13 +3290,14 @@ static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
* (X, N) = src + dest + X;
*/
- tmp = tcg_const_i32(0);
- tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
- tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
+ zero = tcg_constant_i32(0);
+ tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, zero, dest, zero);
+ tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, zero);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
/* Compute signed-overflow for addition. */
+ tmp = tcg_temp_new();
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
tcg_gen_xor_i32(tmp, dest, src);
tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (44 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 45/91] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 47/91] target/m68k: Avoid tcg_const_* throughout Richard Henderson
` (45 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Tidy up the whole function, hoisting is_bfffo as a common test
for whether tlen and tofs needed. Use tcg_constant_i32, and load
a separate temporary for mask.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 42 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 0002d80bf9..e78722fba8 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4027,14 +4027,8 @@ DISAS_INSN(bfop_reg)
TCGv src = DREG(insn, 0);
int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
int ofs = extract32(ext, 6, 5); /* big bit-endian */
- TCGv mask, tofs, tlen;
-
- tofs = NULL;
- tlen = NULL;
- if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
- tofs = tcg_temp_new();
- tlen = tcg_temp_new();
- }
+ TCGv mask, tofs = NULL, tlen = NULL;
+ bool is_bfffo = (insn & 0x0f00) == 0x0d00;
if ((ext & 0x820) == 0) {
/* Immediate width and offset. */
@@ -4045,45 +4039,49 @@ DISAS_INSN(bfop_reg)
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
}
tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
- mask = tcg_const_i32(ror32(maski, ofs));
- if (tofs) {
- tcg_gen_movi_i32(tofs, ofs);
- tcg_gen_movi_i32(tlen, len);
+
+ mask = tcg_constant_i32(ror32(maski, ofs));
+ if (is_bfffo) {
+ tofs = tcg_constant_i32(ofs);
+ tlen = tcg_constant_i32(len);
}
} else {
TCGv tmp = tcg_temp_new();
+
+ mask = tcg_temp_new();
if (ext & 0x20) {
/* Variable width */
tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
tcg_gen_andi_i32(tmp, tmp, 31);
- mask = tcg_const_i32(0x7fffffffu);
- tcg_gen_shr_i32(mask, mask, tmp);
- if (tlen) {
+ tcg_gen_shr_i32(mask, tcg_constant_i32(0x7fffffffu), tmp);
+ if (is_bfffo) {
+ tlen = tcg_temp_new();
tcg_gen_addi_i32(tlen, tmp, 1);
}
} else {
/* Immediate width */
- mask = tcg_const_i32(0x7fffffffu >> (len - 1));
- if (tlen) {
- tcg_gen_movi_i32(tlen, len);
+ tcg_gen_movi_i32(mask, 0x7fffffffu >> (len - 1));
+ if (is_bfffo) {
+ tlen = tcg_constant_i32(len);
}
}
+
if (ext & 0x800) {
/* Variable offset */
tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotr_i32(mask, mask, tmp);
- if (tofs) {
- tcg_gen_mov_i32(tofs, tmp);
+ if (is_bfffo) {
+ tofs = tmp;
}
} else {
/* Immediate offset (and variable width) */
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotri_i32(mask, mask, ofs);
- if (tofs) {
- tcg_gen_movi_i32(tofs, ofs);
+ if (is_bfffo) {
+ tofs = tcg_constant_i32(ofs);
}
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 47/91] target/m68k: Avoid tcg_const_* throughout
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (45 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 48/91] target/mips: Split out gen_lxl Richard Henderson
` (44 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 158 ++++++++++++++++++++--------------------
1 file changed, 77 insertions(+), 81 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index e78722fba8..44c3ac0bc3 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -264,10 +264,7 @@ static void gen_jmp(DisasContext *s, TCGv dest)
static void gen_raise_exception(int nr)
{
- TCGv_i32 tmp;
-
- tmp = tcg_const_i32(nr);
- gen_helper_raise_exception(cpu_env, tmp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr));
}
static void gen_raise_exception_format2(DisasContext *s, int nr,
@@ -471,7 +468,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
if ((ext & 0x80) == 0) {
/* base not suppressed */
if (IS_NULL_QREG(base)) {
- base = tcg_const_i32(offset + bd);
+ base = tcg_constant_i32(offset + bd);
bd = 0;
}
if (!IS_NULL_QREG(add)) {
@@ -487,7 +484,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
add = tmp;
}
} else {
- add = tcg_const_i32(bd);
+ add = tcg_constant_i32(bd);
}
if ((ext & 3) != 0) {
/* memory indirect */
@@ -623,8 +620,7 @@ static void gen_flush_flags(DisasContext *s)
break;
default:
- t0 = tcg_const_i32(s->cc_op);
- gen_helper_flush_flags(cpu_env, t0);
+ gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op));
s->cc_op_synced = 1;
break;
}
@@ -785,14 +781,14 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
switch (reg0) {
case 0: /* Absolute short. */
offset = (int16_t)read_im16(env, s);
- return tcg_const_i32(offset);
+ return tcg_constant_i32(offset);
case 1: /* Absolute long. */
offset = read_im32(env, s);
- return tcg_const_i32(offset);
+ return tcg_constant_i32(offset);
case 2: /* pc displacement */
offset = s->pc;
offset += (int16_t)read_im16(env, s);
- return tcg_const_i32(offset);
+ return tcg_constant_i32(offset);
case 3: /* pc index+displacement. */
return gen_lea_indexed(env, s, NULL_QREG);
case 4: /* Immediate. */
@@ -1167,23 +1163,23 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
}
switch (opsize) {
case OS_BYTE:
- tmp = tcg_const_i32((int8_t)read_im8(env, s));
+ tmp = tcg_constant_i32((int8_t)read_im8(env, s));
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_WORD:
- tmp = tcg_const_i32((int16_t)read_im16(env, s));
+ tmp = tcg_constant_i32((int16_t)read_im16(env, s));
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_LONG:
- tmp = tcg_const_i32(read_im32(env, s));
+ tmp = tcg_constant_i32(read_im32(env, s));
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_SINGLE:
- tmp = tcg_const_i32(read_im32(env, s));
+ tmp = tcg_constant_i32(read_im32(env, s));
gen_helper_extf32(cpu_env, fp, tmp);
break;
case OS_DOUBLE:
- t64 = tcg_const_i64(read_im64(env, s));
+ t64 = tcg_constant_i64(read_im64(env, s));
gen_helper_extf64(cpu_env, fp, t64);
break;
case OS_EXTENDED:
@@ -1191,9 +1187,9 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
- tmp = tcg_const_i32(read_im32(env, s) >> 16);
+ tmp = tcg_constant_i32(read_im32(env, s) >> 16);
tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
- t64 = tcg_const_i64(read_im64(env, s));
+ t64 = tcg_constant_i64(read_im64(env, s));
tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
break;
case OS_PACKED:
@@ -1253,7 +1249,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
goto done;
case 10: /* PL */
case 11: /* MI */
- c->v2 = tcg_const_i32(0);
+ c->v2 = tcg_constant_i32(0);
c->v1 = tmp = tcg_temp_new();
tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
@@ -1269,7 +1265,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
}
}
- c->v2 = tcg_const_i32(0);
+ c->v2 = tcg_constant_i32(0);
switch (cond) {
case 0: /* T */
@@ -2000,7 +1996,7 @@ DISAS_INSN(movem)
addr = tcg_temp_new();
tcg_gen_mov_i32(addr, tmp);
- incr = tcg_const_i32(opsize_bytes(opsize));
+ incr = tcg_constant_i32(opsize_bytes(opsize));
if (is_load) {
/* memory to register */
@@ -2236,13 +2232,13 @@ DISAS_INSN(arith_im)
opsize = insn_opsize(insn);
switch (opsize) {
case OS_BYTE:
- im = tcg_const_i32((int8_t)read_im8(env, s));
+ im = tcg_constant_i32((int8_t)read_im8(env, s));
break;
case OS_WORD:
- im = tcg_const_i32((int16_t)read_im16(env, s));
+ im = tcg_constant_i32((int16_t)read_im16(env, s));
break;
case OS_LONG:
- im = tcg_const_i32(read_im32(env, s));
+ im = tcg_constant_i32(read_im32(env, s));
break;
default:
g_assert_not_reached();
@@ -2394,7 +2390,6 @@ DISAS_INSN(cas2w)
{
uint16_t ext1, ext2;
TCGv addr1, addr2;
- TCGv regs;
/* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
@@ -2426,13 +2421,13 @@ DISAS_INSN(cas2w)
* Dc2 = (R2)
*/
- regs = tcg_const_i32(REG(ext2, 6) |
- (REG(ext1, 6) << 3) |
- (REG(ext2, 0) << 6) |
- (REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
+ TCGv regs = tcg_constant_i32(REG(ext2, 6) |
+ (REG(ext1, 6) << 3) |
+ (REG(ext2, 0) << 6) |
+ (REG(ext1, 0) << 9));
gen_helper_cas2w(cpu_env, regs, addr1, addr2);
}
@@ -2476,10 +2471,10 @@ DISAS_INSN(cas2l)
* Dc2 = (R2)
*/
- regs = tcg_const_i32(REG(ext2, 6) |
- (REG(ext1, 6) << 3) |
- (REG(ext2, 0) << 6) |
- (REG(ext1, 0) << 9));
+ regs = tcg_constant_i32(REG(ext2, 6) |
+ (REG(ext1, 6) << 3) |
+ (REG(ext2, 0) << 6) |
+ (REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
} else {
@@ -2553,7 +2548,7 @@ DISAS_INSN(negx)
* (X, N) = -(src + X);
*/
- z = tcg_const_i32(0);
+ z = tcg_constant_i32(0);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
@@ -2598,8 +2593,7 @@ DISAS_INSN(clr)
int opsize;
TCGv zero;
- zero = tcg_const_i32(0);
-
+ zero = tcg_constant_i32(0);
opsize = insn_opsize(insn);
DEST_EA(env, insn, opsize, zero, NULL);
gen_logic_cc(s, zero, opsize);
@@ -2935,7 +2929,7 @@ DISAS_INSN(jump)
}
if ((insn & 0x40) == 0) {
/* jsr */
- gen_push(s, tcg_const_i32(s->pc));
+ gen_push(s, tcg_constant_i32(s->pc));
}
gen_jmp(s, tmp);
}
@@ -2960,7 +2954,7 @@ DISAS_INSN(addsubq)
if (imm == 0) {
imm = 8;
}
- val = tcg_const_i32(imm);
+ val = tcg_constant_i32(imm);
dest = tcg_temp_new();
tcg_gen_mov_i32(dest, src);
if ((insn & 0x38) == 0x08) {
@@ -3004,7 +2998,7 @@ DISAS_INSN(branch)
}
if (op == 1) {
/* bsr */
- gen_push(s, tcg_const_i32(s->pc));
+ gen_push(s, tcg_constant_i32(s->pc));
}
if (op > 1) {
/* Bcc */
@@ -3153,9 +3147,10 @@ DISAS_INSN(mov3q)
int val;
val = (insn >> 9) & 7;
- if (val == 0)
+ if (val == 0) {
val = -1;
- src = tcg_const_i32(val);
+ }
+ src = tcg_constant_i32(val);
gen_logic_cc(s, src, OS_LONG);
DEST_EA(env, insn, OS_LONG, src, NULL);
}
@@ -3433,7 +3428,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
/* Note that C=0 if shift count is 0, and we get that for free. */
} else {
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
@@ -3455,7 +3450,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
* V = ((s ^ t) & (-1 << (bits - 1))) != 0
*/
if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
- TCGv_i64 tt = tcg_const_i64(32);
+ TCGv_i64 tt = tcg_constant_i64(32);
/* if shift is greater than 32, use 32 */
tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
/* Sign extend the input to 64 bits; re-do the shift. */
@@ -3636,7 +3631,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
{
TCGv X, shl, shr, shx, sz, zero;
- sz = tcg_const_i32(size);
+ sz = tcg_constant_i32(size);
shr = tcg_temp_new();
shl = tcg_temp_new();
@@ -3647,7 +3642,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
/* shx = shx < 0 ? size : shx; */
- zero = tcg_const_i32(0);
+ zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
} else {
tcg_gen_mov_i32(shr, shift); /* shr = shift */
@@ -3726,7 +3721,7 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
/* if shift == 0, register and X are not affected */
- zero = tcg_const_i32(0);
+ zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
@@ -3744,7 +3739,7 @@ DISAS_INSN(rotate_im)
tmp = 8;
}
- shift = tcg_const_i32(tmp);
+ shift = tcg_constant_i32(tmp);
if (insn & 8) {
rotate(DREG(insn, 0), shift, left, 32);
} else {
@@ -3769,7 +3764,7 @@ DISAS_INSN(rotate8_im)
tmp = 8;
}
- shift = tcg_const_i32(tmp);
+ shift = tcg_constant_i32(tmp);
if (insn & 8) {
rotate(reg, shift, left, 8);
} else {
@@ -3793,7 +3788,7 @@ DISAS_INSN(rotate16_im)
tmp = 8;
}
- shift = tcg_const_i32(tmp);
+ shift = tcg_constant_i32(tmp);
if (insn & 8) {
rotate(reg, shift, left, 16);
} else {
@@ -3908,7 +3903,7 @@ DISAS_INSN(rotate_mem)
SRC_EA(env, src, OS_WORD, 0, &addr);
- shift = tcg_const_i32(1);
+ shift = tcg_constant_i32(1);
if (insn & 0x0200) {
rotate(src, shift, left, 16);
} else {
@@ -4002,12 +3997,12 @@ DISAS_INSN(bfext_mem)
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
- len = tcg_const_i32(extract32(ext, 0, 5));
+ len = tcg_constant_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
- ofs = tcg_const_i32(extract32(ext, 6, 5));
+ ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
if (is_sign) {
@@ -4123,12 +4118,12 @@ DISAS_INSN(bfop_mem)
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
- len = tcg_const_i32(extract32(ext, 0, 5));
+ len = tcg_constant_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
- ofs = tcg_const_i32(extract32(ext, 6, 5));
+ ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
switch (insn & 0x0f00) {
@@ -4240,12 +4235,12 @@ DISAS_INSN(bfins_mem)
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
- len = tcg_const_i32(extract32(ext, 0, 5));
+ len = tcg_constant_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
- ofs = tcg_const_i32(extract32(ext, 6, 5));
+ ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
@@ -4378,7 +4373,7 @@ DISAS_INSN(move16_mem)
TCGv reg, addr;
reg = AREG(insn, 0);
- addr = tcg_const_i32(read_im32(env, s));
+ addr = tcg_constant_i32(read_im32(env, s));
if ((insn >> 3) & 1) {
/* MOVE16 (xxx).L, (Ay) */
@@ -4568,14 +4563,14 @@ DISAS_INSN(cf_movec)
} else {
reg = DREG(ext, 12);
}
- gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
+ gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg);
gen_exit_tb(s);
}
DISAS_INSN(m68k_movec)
{
uint16_t ext;
- TCGv reg;
+ TCGv reg, creg;
if (IS_USER(s)) {
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
@@ -4589,10 +4584,11 @@ DISAS_INSN(m68k_movec)
} else {
reg = DREG(ext, 12);
}
+ creg = tcg_constant_i32(ext & 0xfff);
if (insn & 1) {
- gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
+ gen_helper_m68k_movec_to(cpu_env, creg, reg);
} else {
- gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
+ gen_helper_m68k_movec_from(reg, cpu_env, creg);
}
gen_exit_tb(s);
}
@@ -4643,7 +4639,7 @@ DISAS_INSN(pflush)
return;
}
- opmode = tcg_const_i32((insn >> 3) & 3);
+ opmode = tcg_constant_i32((insn >> 3) & 3);
gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
}
@@ -4655,7 +4651,7 @@ DISAS_INSN(ptest)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- is_read = tcg_const_i32((insn >> 5) & 1);
+ is_read = tcg_constant_i32((insn >> 5) & 1);
gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
}
#endif
@@ -4825,7 +4821,7 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
- tmp = tcg_const_i32(read_im32(env, s));
+ tmp = tcg_constant_i32(read_im32(env, s));
gen_store_fcr(s, tmp, mask);
return;
}
@@ -4962,7 +4958,7 @@ DISAS_INSN(fpu)
case 2:
if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
/* fmovecr */
- TCGv rom_offset = tcg_const_i32(opmode);
+ TCGv rom_offset = tcg_constant_i32(opmode);
cpu_dest = gen_fp_ptr(REG(ext, 7));
gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
return;
@@ -5186,7 +5182,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv fpsr;
- c->v2 = tcg_const_i32(0);
+ c->v2 = tcg_constant_i32(0);
/* TODO: Raise BSUN exception. */
fpsr = tcg_temp_new();
gen_load_fcr(s, fpsr, M68K_FPSR);
@@ -5406,7 +5402,7 @@ DISAS_INSN(fsave)
if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
/* always write IDLE */
- TCGv idle = tcg_const_i32(0x41000000);
+ TCGv idle = tcg_constant_i32(0x41000000);
DEST_EA(env, insn, OS_LONG, idle, NULL);
} else {
disas_undef(env, s, insn);
@@ -5536,7 +5532,7 @@ DISAS_INSN(mac)
/* Skip the accumulate if the value is already saturated. */
l1 = gen_new_label();
tmp = tcg_temp_new();
- gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
+ gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc));
gen_op_jmp_nz32(tmp, l1);
}
#endif
@@ -5547,11 +5543,11 @@ DISAS_INSN(mac)
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
- gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
+ gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
- gen_helper_macsats(cpu_env, tcg_const_i32(acc));
+ gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
else
- gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
+ gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
@@ -5570,7 +5566,7 @@ DISAS_INSN(mac)
/* Skip the accumulate if the value is already saturated. */
l1 = gen_new_label();
tmp = tcg_temp_new();
- gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
+ gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc));
gen_op_jmp_nz32(tmp, l1);
}
#endif
@@ -5579,18 +5575,18 @@ DISAS_INSN(mac)
else
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
- gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
+ gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
- gen_helper_macsats(cpu_env, tcg_const_i32(acc));
+ gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
else
- gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
+ gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
if (l1 != -1)
gen_set_label(l1);
#endif
}
- gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
+ gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc));
if (insn & 0x30) {
TCGv rw;
@@ -5640,8 +5636,8 @@ DISAS_INSN(move_mac)
int src;
TCGv dest;
src = insn & 3;
- dest = tcg_const_i32((insn >> 9) & 3);
- gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
+ dest = tcg_constant_i32((insn >> 9) & 3);
+ gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src));
gen_mac_clear_flags();
gen_helper_mac_set_flags(cpu_env, dest);
}
@@ -5666,7 +5662,7 @@ DISAS_INSN(from_mext)
TCGv reg;
TCGv acc;
reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
- acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
+ acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
gen_helper_get_mac_extf(reg, cpu_env, acc);
else
@@ -5701,7 +5697,7 @@ DISAS_INSN(to_mac)
}
tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
gen_mac_clear_flags();
- gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
+ gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum));
}
DISAS_INSN(to_macsr)
@@ -5724,7 +5720,7 @@ DISAS_INSN(to_mext)
TCGv val;
TCGv acc;
SRC_EA(env, val, OS_LONG, 0, NULL);
- acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
+ acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
gen_helper_set_mac_extf(cpu_env, val, acc);
else if (s->env->macsr & MACSR_SU)
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 48/91] target/mips: Split out gen_lxl
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (46 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 47/91] target/m68k: Avoid tcg_const_* throughout Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 49/91] target/mips: Split out gen_lxr Richard Henderson
` (43 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Common subroutine for LDL and LWL.
Use tcg_constant_tl instead of tcg_const_tl and t2.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 106 ++++++++++++------------------------
1 file changed, 36 insertions(+), 70 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 0fa9634d39..05c8d4ce44 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1995,6 +1995,32 @@ static target_ulong pc_relative_pc(DisasContext *ctx)
return pc;
}
+/* LWL or LDL, depending on MemOp. */
+static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr,
+ int mem_idx, MemOp mop)
+{
+ int sizem1 = memop_size(mop) - 1;
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ /*
+ * Do a byte access to possibly trigger a page
+ * fault with the unaligned address.
+ */
+ tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, addr, sizem1);
+ if (!cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, sizem1);
+ }
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, addr, ~sizem1);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop);
+ tcg_gen_shl_tl(t0, t0, t1);
+ tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1);
+ tcg_gen_andc_tl(t1, reg, t1);
+ tcg_gen_or_tl(reg, t0, t1);
+}
+
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
@@ -2034,25 +2060,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LDL:
t1 = tcg_temp_new();
- /*
- * Do a byte access to possibly trigger a page
- * fault with the unaligned address.
- */
- tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 7);
- if (!cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 7);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~7);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
- tcg_gen_shl_tl(t0, t0, t1);
- t2 = tcg_const_tl(-1);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
- tcg_gen_andc_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- gen_store_gpr(t0, rt);
+ gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_store_gpr(t1, rt);
break;
case OPC_LDR:
t1 = tcg_temp_new();
@@ -2133,26 +2143,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
/* fall through */
case OPC_LWL:
t1 = tcg_temp_new();
- /*
- * Do a byte access to possibly trigger a page
- * fault with the unaligned address.
- */
- tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 3);
- if (!cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 3);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~3);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
- tcg_gen_shl_tl(t0, t0, t1);
- t2 = tcg_const_tl(-1);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
- tcg_gen_andc_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_ext32s_tl(t0, t0);
- gen_store_gpr(t0, rt);
+ gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL);
+ tcg_gen_ext32s_tl(t1, t1);
+ gen_store_gpr(t1, rt);
break;
case OPC_LWRE:
mem_idx = MIPS_HFLAG_UM;
@@ -4220,28 +4214,12 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLWLC1:
check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, shf_offset);
- t1 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 3);
- if (!cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 3);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~3);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
- tcg_gen_shl_tl(t0, t0, t1);
- t2 = tcg_const_tl(-1);
- tcg_gen_shl_tl(t2, t2, t1);
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
+ t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- tcg_gen_andc_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
-#if defined(TARGET_MIPS64)
- tcg_gen_extrl_i64_i32(fp0, t0);
-#else
- tcg_gen_ext32s_tl(fp0, t0);
-#endif
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
case OPC_GSLWRC1:
@@ -4277,21 +4255,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 7);
- if (!cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 7);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~7);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
- tcg_gen_shl_tl(t0, t0, t1);
- t2 = tcg_const_tl(-1);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_andc_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- gen_store_fpr64(ctx, t0, rt);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_store_fpr64(ctx, t1, rt);
break;
case OPC_GSLDRC1:
check_cp1_enabled(ctx);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 49/91] target/mips: Split out gen_lxr
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (47 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 48/91] target/mips: Split out gen_lxl Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 50/91] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
` (42 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Common subroutine for LDR and LWR.
Use tcg_constant_tl of ~1 instead of tcg_const_tl of 0x..fe.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 116 +++++++++++++-----------------------
1 file changed, 40 insertions(+), 76 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 05c8d4ce44..7018c427be 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2021,11 +2021,39 @@ static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr,
tcg_gen_or_tl(reg, t0, t1);
}
+/* LWR or LDR, depending on MemOp. */
+static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
+ int mem_idx, MemOp mop)
+{
+ int size = memop_size(mop);
+ int sizem1 = size - 1;
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ /*
+ * Do a byte access to possibly trigger a page
+ * fault with the unaligned address.
+ */
+ tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, addr, sizem1);
+ if (cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, sizem1);
+ }
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, addr, ~sizem1);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop);
+ tcg_gen_shr_tl(t0, t0, t1);
+ tcg_gen_xori_tl(t1, t1, size * 8 - 1);
+ tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1);
+ tcg_gen_and_tl(t1, reg, t1);
+ tcg_gen_or_tl(reg, t0, t1);
+}
+
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
{
- TCGv t0, t1, t2;
+ TCGv t0, t1;
int mem_idx = ctx->mem_idx;
if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
@@ -2066,26 +2094,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LDR:
t1 = tcg_temp_new();
- /*
- * Do a byte access to possibly trigger a page
- * fault with the unaligned address.
- */
- tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 7);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 7);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~7);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 63);
- t2 = tcg_const_tl(0xfffffffffffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- gen_store_gpr(t0, rt);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_const_tl(pc_relative_pc(ctx));
@@ -2153,27 +2164,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
/* fall through */
case OPC_LWR:
t1 = tcg_temp_new();
- /*
- * Do a byte access to possibly trigger a page
- * fault with the unaligned address.
- */
- tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 3);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 3);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~3);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 31);
- t2 = tcg_const_tl(0xfffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_ext32s_tl(t0, t0);
- gen_store_gpr(t0, rt);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL);
+ tcg_gen_ext32s_tl(t1, t1);
+ gen_store_gpr(t1, rt);
break;
case OPC_LLE:
mem_idx = MIPS_HFLAG_UM;
@@ -4150,7 +4144,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
static void gen_loongson_lswc2(DisasContext *ctx, int rt,
int rs, int rd)
{
- TCGv t0, t1, t2;
+ TCGv t0, t1;
TCGv_i32 fp0;
#if defined(TARGET_MIPS64)
int lsq_rt1 = ctx->opcode & 0x1f;
@@ -4225,29 +4219,12 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLWRC1:
check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, shf_offset);
- t1 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 3);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 3);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~3);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 31);
- t2 = tcg_const_tl(0xfffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
+ t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
-#if defined(TARGET_MIPS64)
- tcg_gen_extrl_i64_i32(fp0, t0);
-#else
- tcg_gen_ext32s_tl(fp0, t0);
-#endif
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
#if defined(TARGET_MIPS64)
@@ -4263,22 +4240,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 7);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 7);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~7);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 63);
- t2 = tcg_const_tl(0xfffffffffffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- gen_store_fpr64(ctx, t0, rt);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_store_fpr64(ctx, t1, rt);
break;
#endif
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 50/91] target/mips: Avoid tcg_const_tl in gen_r6_ld
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (48 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 49/91] target/mips: Split out gen_lxr Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 51/91] target/mips: Avoid tcg_const_* throughout Richard Henderson
` (41 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Allocate a separate temp for modification.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 7018c427be..bbc2212660 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2964,8 +2964,8 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
static inline void gen_r6_ld(target_long addr, int reg, int memidx,
MemOp memop)
{
- TCGv t0 = tcg_const_tl(addr);
- tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop);
gen_store_gpr(t0, reg);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 51/91] target/mips: Avoid tcg_const_* throughout
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (49 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 50/91] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 52/91] target/ppc: Split out gen_vx_vmul10 Richard Henderson
` (40 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/mxu_translate.c | 4 +-
target/mips/tcg/translate.c | 56 +++++++++++------------
target/mips/tcg/tx79_translate.c | 4 +-
target/mips/tcg/micromips_translate.c.inc | 4 +-
target/mips/tcg/nanomips_translate.c.inc | 16 ++++---
5 files changed, 43 insertions(+), 41 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 8703b0cef4..bdd20709c0 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1072,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do half-word-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_const_i32(0);
+ TCGv_i32 t1 = tcg_constant_i32(0);
/* the left half-word first */
tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
@@ -1163,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do byte-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_const_i32(0);
+ TCGv_i32 t1 = tcg_constant_i32(0);
int32_t i;
/* the leftmost byte (byte 3) first */
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index bbc2212660..1fb4ef7127 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2099,14 +2099,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
- t1 = tcg_const_tl(pc_relative_pc(ctx));
+ t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
- t1 = tcg_const_tl(pc_relative_pc(ctx));
+ t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
gen_store_gpr(t0, rt);
@@ -2733,7 +2733,7 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc,
t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
- t1 = tcg_const_tl(0);
+ t1 = tcg_constant_tl(0);
t2 = tcg_temp_new();
gen_load_gpr(t2, rs);
switch (opc) {
@@ -3084,8 +3084,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_DIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3095,8 +3095,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_MODU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3175,16 +3175,16 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_DDIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
}
break;
case R6_OPC_DMODU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
}
@@ -3248,8 +3248,8 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
break;
case MMI_OPC_DIVU1:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3304,8 +3304,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
case OPC_DIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@@ -3355,8 +3355,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
case OPC_DDIVU:
{
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
@@ -4916,7 +4916,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_WSBH:
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0x00FF00FF);
+ TCGv t2 = tcg_constant_tl(0x00FF00FF);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_and_tl(t1, t1, t2);
@@ -4936,7 +4936,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSBH:
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
+ TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_and_tl(t1, t1, t2);
@@ -4948,7 +4948,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSHD:
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
+ TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
tcg_gen_shri_tl(t1, t0, 16);
tcg_gen_and_tl(t1, t1, t2);
@@ -8459,7 +8459,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 5:
case 6:
case 7:
- gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
+ gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel));
break;
default:
goto die;
@@ -9485,7 +9485,7 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
int fs)
{
- TCGv_i32 t1 = tcg_const_i32(0);
+ TCGv_i32 t1 = tcg_constant_i32(0);
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
TCGv_i32 fp2 = tcg_temp_new_i32();
@@ -9518,7 +9518,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
int fs)
{
- TCGv_i64 t1 = tcg_const_i64(0);
+ TCGv_i64 t1 = tcg_constant_i64(0);
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
TCGv_i64 fp2 = tcg_temp_new_i64();
@@ -11516,7 +11516,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
int16_t offset)
{
- TCGv_i32 t0 = tcg_const_i32(op);
+ TCGv_i32 t0 = tcg_constant_i32(op);
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
gen_helper_cache(cpu_env, t1, t0);
@@ -11860,7 +11860,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_PH_W:
check_dsp_r2(ctx);
{
- TCGv_i32 sa_t = tcg_const_i32(v2);
+ TCGv_i32 sa_t = tcg_constant_i32(v2);
gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
break;
@@ -11868,7 +11868,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_R_PH_W:
check_dsp_r2(ctx);
{
- TCGv_i32 sa_t = tcg_const_i32(v2);
+ TCGv_i32 sa_t = tcg_constant_i32(v2);
gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
break;
@@ -12057,14 +12057,14 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_QH_PW:
check_dsp_r2(ctx);
{
- TCGv_i32 ret_t = tcg_const_i32(ret);
+ TCGv_i32 ret_t = tcg_constant_i32(ret);
gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
break;
}
case OPC_PRECR_SRA_R_QH_PW:
check_dsp_r2(ctx);
{
- TCGv_i32 sa_v = tcg_const_i32(ret);
+ TCGv_i32 sa_v = tcg_constant_i32(ret);
gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
break;
}
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index d46bc73972..3a45a1bfea 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -243,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
return true;
}
- c0 = tcg_const_tl(0);
- c1 = tcg_const_tl(0xffffffff);
+ c0 = tcg_constant_tl(0);
+ c1 = tcg_constant_tl(0xffffffff);
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 23f80d4315..e8b193aeda 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
gen_base_offset_addr(ctx, t0, base, offset);
- t1 = tcg_const_tl(reglist);
- t2 = tcg_const_i32(ctx->mem_idx);
+ t1 = tcg_constant_tl(reglist);
+ t2 = tcg_constant_i32(ctx->mem_idx);
save_cpu_state(ctx, 1);
switch (opc) {
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index b3df7fec40..9398e28000 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -3359,7 +3359,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 0:
/* PRECR_SRA_PH_W */
{
- TCGv_i32 sa_t = tcg_const_i32(rd);
+ TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
@@ -3368,7 +3368,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 1:
/* PRECR_SRA_R_PH_W */
{
- TCGv_i32 sa_t = tcg_const_i32(rd);
+ TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
@@ -3864,10 +3864,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_nms(ctx);
if (rt != 0) {
TCGv t0 = tcg_temp_new();
- TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
- TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
- << 1);
- TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));
+ TCGv_i32 shift =
+ tcg_constant_i32(extract32(ctx->opcode, 0, 5));
+ TCGv_i32 shiftx =
+ tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1);
+ TCGv_i32 stripe =
+ tcg_constant_i32(extract32(ctx->opcode, 6, 1));
gen_load_gpr(t0, rs);
gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
@@ -4500,7 +4502,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
/* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) {
- TCGv tmp = tcg_const_tl(ctx->base.pc_next);
+ TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
generate_exception_end(ctx, EXCP_AdEL);
return 2;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 52/91] target/ppc: Split out gen_vx_vmul10
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (50 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 51/91] target/mips: Avoid tcg_const_* throughout Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
` (39 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Move the body out of this large macro.
Use tcg_constant_i64.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vmx-impl.c.inc | 95 +++++++++++++++--------------
1 file changed, 49 insertions(+), 46 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 05ba9c9492..ee656d6a44 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -171,53 +171,56 @@ static void gen_mtvscr(DisasContext *ctx)
gen_helper_mtvscr(cpu_env, val);
}
+static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ TCGv_i64 t2;
+ TCGv_i64 avr;
+ TCGv_i64 ten, z;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+ avr = tcg_temp_new_i64();
+ ten = tcg_constant_i64(10);
+ z = tcg_constant_i64(0);
+
+ if (add_cin) {
+ get_avr64(avr, rA(ctx->opcode), false);
+ tcg_gen_mulu2_i64(t0, t1, avr, ten);
+ get_avr64(avr, rB(ctx->opcode), false);
+ tcg_gen_andi_i64(t2, avr, 0xF);
+ tcg_gen_add2_i64(avr, t2, t0, t1, t2, z);
+ set_avr64(rD(ctx->opcode), avr, false);
+ } else {
+ get_avr64(avr, rA(ctx->opcode), false);
+ tcg_gen_mulu2_i64(avr, t2, avr, ten);
+ set_avr64(rD(ctx->opcode), avr, false);
+ }
+
+ if (ret_carry) {
+ get_avr64(avr, rA(ctx->opcode), true);
+ tcg_gen_mulu2_i64(t0, t1, avr, ten);
+ tcg_gen_add2_i64(t0, avr, t0, t1, t2, z);
+ set_avr64(rD(ctx->opcode), avr, false);
+ set_avr64(rD(ctx->opcode), z, true);
+ } else {
+ get_avr64(avr, rA(ctx->opcode), true);
+ tcg_gen_mul_i64(t0, avr, ten);
+ tcg_gen_add_i64(avr, t0, t2);
+ set_avr64(rD(ctx->opcode), avr, true);
+ }
+}
+
#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
- TCGv_i64 avr; \
- TCGv_i64 ten, z; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- avr = tcg_temp_new_i64(); \
- ten = tcg_const_i64(10); \
- z = tcg_const_i64(0); \
- \
- if (add_cin) { \
- get_avr64(avr, rA(ctx->opcode), false); \
- tcg_gen_mulu2_i64(t0, t1, avr, ten); \
- get_avr64(avr, rB(ctx->opcode), false); \
- tcg_gen_andi_i64(t2, avr, 0xF); \
- tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
- set_avr64(rD(ctx->opcode), avr, false); \
- } else { \
- get_avr64(avr, rA(ctx->opcode), false); \
- tcg_gen_mulu2_i64(avr, t2, avr, ten); \
- set_avr64(rD(ctx->opcode), avr, false); \
- } \
- \
- if (ret_carry) { \
- get_avr64(avr, rA(ctx->opcode), true); \
- tcg_gen_mulu2_i64(t0, t1, avr, ten); \
- tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
- set_avr64(rD(ctx->opcode), avr, false); \
- set_avr64(rD(ctx->opcode), z, true); \
- } else { \
- get_avr64(avr, rA(ctx->opcode), true); \
- tcg_gen_mul_i64(t0, avr, ten); \
- tcg_gen_add_i64(avr, t0, t2); \
- set_avr64(rD(ctx->opcode), avr, true); \
- } \
-} \
+ static void glue(gen_, name)(DisasContext *ctx) \
+ { gen_vx_vmul10(ctx, add_cin, ret_carry); }
GEN_VX_VMUL10(vmul10uq, 0, 0);
GEN_VX_VMUL10(vmul10euq, 1, 0);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (51 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 52/91] target/ppc: Split out gen_vx_vmul10 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 54/91] target/rx: Use tcg_gen_abs_i32 Richard Henderson
` (38 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vmx-impl.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index ee656d6a44..7af6d7217d 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -906,7 +906,6 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- t1 = tcg_const_i64(0);
get_avr64(lo, a->vra, false);
get_avr64(hi, a->vra, true);
@@ -917,7 +916,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
if (right) {
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
if (alg) {
+ t1 = tcg_temp_new_i64();
tcg_gen_sari_i64(t1, lo, 63);
+ } else {
+ t1 = zero;
}
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 54/91] target/rx: Use tcg_gen_abs_i32
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (52 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 55/91] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
` (37 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Remove the local definition of rx_abs.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/translate.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 6624414739..998e6e0b7e 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -1126,21 +1126,11 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
return true;
}
-static void rx_abs(TCGv ret, TCGv arg1)
-{
- TCGv neg;
- TCGv zero;
- neg = tcg_temp_new();
- zero = tcg_const_i32(0);
- tcg_gen_neg_i32(neg, arg1);
- tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1);
-}
-
/* abs rd */
/* abs rs, rd */
static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
{
- rx_gen_op_rr(rx_abs, a->rd, a->rs);
+ rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 55/91] target/rx: Use cpu_psw_z as temp in flags computation
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (53 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 54/91] target/rx: Use tcg_gen_abs_i32 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 56/91] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
` (36 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Since PSW_Z = PSW_S, we can move that assignment to the end
and use PSW_Z as a temporary while computing PSW_O.
Use tcg_constant_i32 instead of tcg_const_i32.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/translate.c | 28 +++++++++++++---------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 998e6e0b7e..c47aa26893 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
/* ret = arg1 + arg2 + psw_c */
static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
{
- TCGv z;
- z = tcg_const_i32(0);
+ TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
- tcg_gen_xor_i32(z, arg1, arg2);
- tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
+ tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
+ tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
+ tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}
@@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
/* ret = arg1 + arg2 */
static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
{
- TCGv z;
- z = tcg_const_i32(0);
+ TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
- tcg_gen_xor_i32(z, arg1, arg2);
- tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
+ tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
+ tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
+ tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}
@@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
/* ret = arg1 - arg2 */
static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
{
- TCGv temp;
tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
- temp = tcg_temp_new_i32();
- tcg_gen_xor_i32(temp, arg1, arg2);
- tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
+ tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
+ tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
+ tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
/* CMP not required return */
if (ret) {
tcg_gen_mov_i32(ret, cpu_psw_s);
}
}
+
static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
{
rx_sub(NULL, arg1, arg2);
}
+
/* ret = arg1 - arg2 - !psw_c */
/* -> ret = arg1 + ~arg2 + psw_c */
static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 56/91] target/rx: Avoid tcg_const_i32 when new temp needed
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (54 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 55/91] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 57/91] target/rx: Avoid tcg_const_i32 Richard Henderson
` (35 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
These three cases use a constant as first input, and
then overwrite the temp in the output. Separate them.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index c47aa26893..6b218d5d5e 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -1313,10 +1313,10 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
done = gen_new_label();
/* if (cpu_regs[a->rs]) { */
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
- count = tcg_const_i32(32);
+ count = tcg_temp_new();
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
- tcg_gen_sub_i32(count, count, tmp);
+ tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp);
tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
@@ -1979,10 +1979,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _rr) * a) \
{ \
TCGv mask, b; \
- mask = tcg_const_i32(1); \
+ mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
- tcg_gen_shl_i32(mask, mask, b); \
+ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
@@ -1990,10 +1990,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _rm) * a) \
{ \
TCGv mask, mem, addr, b; \
- mask = tcg_const_i32(1); \
+ mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
- tcg_gen_shl_i32(mask, mask, b); \
+ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
mem = tcg_temp_new(); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 57/91] target/rx: Avoid tcg_const_i32
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (55 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 56/91] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 58/91] target/s390x: Avoid tcg_const_i64 Richard Henderson
` (34 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 6b218d5d5e..70fad98e93 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
{
TCGv imm, mem;
- imm = tcg_const_i32(a->imm);
+ imm = tcg_constant_i32(a->imm);
mem = tcg_temp_new();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
rx_gen_st(a->sz, imm, mem);
@@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm)
{
TCGv z;
TCGv _imm;
- z = tcg_const_i32(0);
- _imm = tcg_const_i32(imm);
+ z = tcg_constant_i32(0);
+ _imm = tcg_constant_i32(imm);
tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
_imm, cpu_regs[rd]);
}
@@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
{
- TCGv imm = tcg_const_i32(src2);
+ TCGv imm = tcg_constant_i32(src2);
opr(cpu_regs[dst], cpu_regs[src], imm);
}
@@ -1188,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
/* emul #imm, rd */
static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
{
- TCGv imm = tcg_const_i32(a->imm);
+ TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@@ -1215,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
/* emulu #imm, rd */
static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
{
- TCGv imm = tcg_const_i32(a->imm);
+ TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@@ -1585,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
static inline void rx_save_pc(DisasContext *ctx)
{
- TCGv pc = tcg_const_i32(ctx->base.pc_next);
+ TCGv pc = tcg_constant_i32(ctx->base.pc_next);
push(pc);
}
@@ -1668,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
#define STRING(op) \
do { \
- TCGv size = tcg_const_i32(a->sz); \
+ TCGv size = tcg_constant_i32(a->sz); \
gen_helper_##op(cpu_env, size); \
} while (0)
@@ -1799,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
/* racw #imm */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{
- TCGv imm = tcg_const_i32(a->imm + 1);
+ TCGv imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(cpu_env, imm);
return true;
}
@@ -1809,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
{
TCGv tmp, z;
tmp = tcg_temp_new();
- z = tcg_const_i32(0);
+ z = tcg_constant_i32(0);
/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
/* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
@@ -1831,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \
{ \
- TCGv imm = tcg_const_i32(li(ctx, 0)); \
+ TCGv imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \
cpu_regs[a->rd], imm); \
return true; \
@@ -1865,7 +1865,7 @@ FOP(FDIV, fdiv)
/* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
- TCGv imm = tcg_const_i32(li(ctx, 0));
+ TCGv imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
return true;
}
@@ -1962,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
{ \
TCGv mask, mem, addr; \
mem = tcg_temp_new(); \
- mask = tcg_const_i32(1 << a->imm); \
+ mask = tcg_constant_i32(1 << a->imm); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
return true; \
@@ -1971,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _ir) * a) \
{ \
TCGv mask; \
- mask = tcg_const_i32(1 << a->imm); \
+ mask = tcg_constant_i32(1 << a->imm); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
@@ -2116,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
{
TCGv imm;
- imm = tcg_const_i32(a->imm);
+ imm = tcg_constant_i32(a->imm);
move_to_cr(ctx, imm, a->cr);
return true;
}
@@ -2178,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
TCGv vec;
tcg_debug_assert(a->imm < 0x100);
- vec = tcg_const_i32(a->imm);
+ vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxint(cpu_env, vec);
ctx->base.is_jmp = DISAS_NORETURN;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 58/91] target/s390x: Avoid tcg_const_i64
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (56 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 57/91] target/rx: Avoid tcg_const_i32 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 59/91] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
` (33 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 7969051ce9..32d61fc40d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4857,13 +4857,13 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o)
static DisasJumpType op_zero(DisasContext *s, DisasOps *o)
{
- o->out = tcg_const_i64(0);
+ o->out = tcg_constant_i64(0);
return DISAS_NEXT;
}
static DisasJumpType op_zero2(DisasContext *s, DisasOps *o)
{
- o->out = tcg_const_i64(0);
+ o->out = tcg_constant_i64(0);
o->out2 = o->out;
return DISAS_NEXT;
}
@@ -5762,7 +5762,7 @@ static void in2_sh(DisasContext *s, DisasOps *o)
int d2 = get_field(s, d2);
if (b2 == 0) {
- o->in2 = tcg_const_i64(d2 & 0x3f);
+ o->in2 = tcg_constant_i64(d2 & 0x3f);
} else {
o->in2 = get_address(s, 0, b2, d2);
tcg_gen_andi_i64(o->in2, o->in2, 0x3f);
@@ -5868,46 +5868,46 @@ static void in2_mri2_64(DisasContext *s, DisasOps *o)
static void in2_i2(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64(get_field(s, i2));
+ o->in2 = tcg_constant_i64(get_field(s, i2));
}
#define SPEC_in2_i2 0
static void in2_i2_8u(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64((uint8_t)get_field(s, i2));
+ o->in2 = tcg_constant_i64((uint8_t)get_field(s, i2));
}
#define SPEC_in2_i2_8u 0
static void in2_i2_16u(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64((uint16_t)get_field(s, i2));
+ o->in2 = tcg_constant_i64((uint16_t)get_field(s, i2));
}
#define SPEC_in2_i2_16u 0
static void in2_i2_32u(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64((uint32_t)get_field(s, i2));
+ o->in2 = tcg_constant_i64((uint32_t)get_field(s, i2));
}
#define SPEC_in2_i2_32u 0
static void in2_i2_16u_shl(DisasContext *s, DisasOps *o)
{
uint64_t i2 = (uint16_t)get_field(s, i2);
- o->in2 = tcg_const_i64(i2 << s->insn->data);
+ o->in2 = tcg_constant_i64(i2 << s->insn->data);
}
#define SPEC_in2_i2_16u_shl 0
static void in2_i2_32u_shl(DisasContext *s, DisasOps *o)
{
uint64_t i2 = (uint32_t)get_field(s, i2);
- o->in2 = tcg_const_i64(i2 << s->insn->data);
+ o->in2 = tcg_constant_i64(i2 << s->insn->data);
}
#define SPEC_in2_i2_32u_shl 0
#ifndef CONFIG_USER_ONLY
static void in2_insn(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64(s->fields.raw_insn);
+ o->in2 = tcg_constant_i64(s->fields.raw_insn);
}
#define SPEC_in2_insn 0
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 59/91] target/sh4: Avoid tcg_const_i32 for TAS.B
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (57 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 58/91] target/s390x: Avoid tcg_const_i64 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 60/91] target/sh4: Avoid tcg_const_i32 Richard Henderson
` (32 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Since we're assigning to cpu_sr_t in the end,
use that as the intermediate temp as well.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ad6de41712..70a45c26e8 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1610,12 +1610,9 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
return;
case 0x401b: /* tas.b @Rn */
- {
- TCGv val = tcg_const_i32(0x80);
- tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val,
- ctx->memidx, MO_UB);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
- }
+ tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8),
+ tcg_constant_i32(0x80), ctx->memidx, MO_UB);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0);
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 60/91] target/sh4: Avoid tcg_const_i32
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (58 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 59/91] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 61/91] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
` (31 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 70a45c26e8..97da8bce48 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -526,13 +526,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
{
- TCGv addr = tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2);
+ TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
}
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
{
- TCGv addr = tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
+ TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
}
return;
@@ -694,7 +694,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x300e: /* addc Rm,Rn */
{
TCGv t0, t1;
- t0 = tcg_const_tl(0);
+ t0 = tcg_constant_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
@@ -754,7 +754,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- TCGv zero = tcg_const_i32(0);
+ TCGv zero = tcg_constant_i32(0);
/* shift left arg1, saving the bit being pushed out and inserting
T on the right */
@@ -849,7 +849,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x600a: /* negc Rm,Rn */
{
- TCGv t0 = tcg_const_i32(0);
+ TCGv t0 = tcg_constant_i32(0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
REG(B7_4), t0, cpu_sr_t, t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
@@ -913,7 +913,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x300a: /* subc Rm,Rn */
{
TCGv t0, t1;
- t0 = tcg_const_tl(0);
+ t0 = tcg_constant_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
@@ -1242,7 +1242,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv imm;
CHECK_NOT_DELAY_SLOT
gen_save_cpu_state(ctx, true);
- imm = tcg_const_i32(B7_0);
+ imm = tcg_constant_i32(B7_0);
gen_helper_trapa(cpu_env, imm);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -1709,8 +1709,8 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_1
{
- TCGv m = tcg_const_i32((ctx->opcode >> 8) & 3);
- TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3);
+ TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3);
+ TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_fipr(cpu_env, m, n);
return;
}
@@ -1722,7 +1722,7 @@ static void _decode_opc(DisasContext * ctx)
if ((ctx->opcode & 0x0300) != 0x0100) {
goto do_illegal;
}
- TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3);
+ TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_ftrv(cpu_env, n);
return;
}
@@ -1926,7 +1926,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
op_dst = B11_8;
op_opc = INDEX_op_xor_i32;
- op_arg = tcg_const_i32(-1);
+ op_arg = tcg_constant_i32(-1);
break;
case 0x7000 ... 0x700f: /* add #imm,Rn */
@@ -1934,7 +1934,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_opc = INDEX_op_add_i32;
- op_arg = tcg_const_i32(B7_0s);
+ op_arg = tcg_constant_i32(B7_0s);
break;
case 0x3000: /* cmp/eq Rm,Rn */
@@ -1980,7 +1980,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_opc = INDEX_op_setcond_i32;
- op_arg = tcg_const_i32(0);
+ op_arg = tcg_constant_i32(0);
NEXT_INSN;
if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 61/91] tcg/sparc: Avoid tcg_const_tl in gen_edge
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (59 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 60/91] target/sh4: Avoid tcg_const_i32 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 62/91] target/tricore: Split t_n as constant from temp as variable Richard Henderson
` (30 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Push tcg_constant_tl into the shift argument directly.
Since t1 no longer exists as a temp, replace with lo1,
whose last use was just above.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 5ee293326c..137bdc5159 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2838,7 +2838,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
int width, bool cc, bool left)
{
- TCGv lo1, lo2, t1, t2;
+ TCGv lo1, lo2;
uint64_t amask, tabl, tabr;
int shift, imask, omask;
@@ -2905,10 +2905,8 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
tcg_gen_shli_tl(lo1, lo1, shift);
tcg_gen_shli_tl(lo2, lo2, shift);
- t1 = tcg_const_tl(tabl);
- t2 = tcg_const_tl(tabr);
- tcg_gen_shr_tl(lo1, t1, lo1);
- tcg_gen_shr_tl(lo2, t2, lo2);
+ tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
+ tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
tcg_gen_andi_tl(dst, lo1, omask);
tcg_gen_andi_tl(lo2, lo2, omask);
@@ -2927,9 +2925,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
lo2 |= -(s1 == s2)
dst &= lo2
*/
- tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
- tcg_gen_neg_tl(t1, t1);
- tcg_gen_or_tl(lo2, lo2, t1);
+ tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2);
+ tcg_gen_neg_tl(lo1, lo1);
+ tcg_gen_or_tl(lo2, lo2, lo1);
tcg_gen_and_tl(dst, dst, lo2);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 62/91] target/tricore: Split t_n as constant from temp as variable
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (60 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 61/91] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 63/91] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
` (29 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
As required, allocate temp separately.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 268 +++++++++++++++++++------------------
1 file changed, 140 insertions(+), 128 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 127f9a989a..194bef27a6 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -595,21 +595,22 @@ static inline void
gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -621,21 +622,22 @@ static inline void
gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -647,22 +649,22 @@ static inline void
gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
@@ -682,23 +684,24 @@ static inline void
gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -718,23 +721,24 @@ static inline void
gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -752,22 +756,22 @@ static inline void
gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
@@ -785,22 +789,22 @@ static inline void
gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
@@ -813,21 +817,21 @@ static inline void
gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
@@ -839,20 +843,20 @@ static inline void
gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
@@ -872,21 +876,22 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
static inline void
gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
@@ -899,20 +904,20 @@ static inline void
gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
@@ -932,21 +937,22 @@ gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
static inline void
gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
@@ -957,15 +963,15 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
static inline void
gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
- TCGv temp = tcg_const_i32(n);
- gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
+ TCGv t_n = tcg_constant_i32(n);
+ gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n);
}
static inline void
gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
- TCGv temp = tcg_const_i32(n);
- gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
+ TCGv t_n = tcg_constant_i32(n);
+ gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n);
}
static inline void
@@ -1176,10 +1182,10 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv_i64 r1 = tcg_temp_new_i64();
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
- gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
+ gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1);
}
@@ -1516,21 +1522,22 @@ static inline void
gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -1542,23 +1549,24 @@ static inline void
gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -1576,22 +1584,22 @@ static inline void
gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
@@ -1604,21 +1612,21 @@ static inline void
gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
@@ -1630,20 +1638,20 @@ static inline void
gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
@@ -1664,20 +1672,20 @@ static inline void
gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
@@ -1912,10 +1920,10 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv_i64 r1 = tcg_temp_new_i64();
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
- gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
+ gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1);
}
@@ -1923,21 +1931,22 @@ static inline void
gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -1949,22 +1958,22 @@ static inline void
gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
@@ -1981,21 +1990,22 @@ gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
static inline void
gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
@@ -2007,23 +2017,24 @@ static inline void
gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
@@ -2041,22 +2052,22 @@ static inline void
gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
@@ -2072,21 +2083,22 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
static inline void
gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv t_n = tcg_constant_i32(n);
+ TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
- GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_LU:
- GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UL:
- GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
break;
case MODE_UU:
- GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
+ GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 63/91] target/tricore: Rename t_off10 and use tcg_constant_i32
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (61 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 62/91] target/tricore: Split t_n as constant from temp as variable Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 64/91] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
` (28 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
While temp3 could simply be initialized with tcg_constant_i32,
the renaming makes the purpose clearer.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 56 ++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 29 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 194bef27a6..19cf4b6cc7 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -4380,7 +4380,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
- TCGv temp, temp2, temp3;
+ TCGv temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
@@ -4389,7 +4389,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- temp3 = tcg_const_i32(off10);
+ t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
@@ -4403,7 +4403,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
case OPC2_32_BO_CACHEA_WI_CIRC:
case OPC2_32_BO_CACHEA_W_CIRC:
case OPC2_32_BO_CACHEA_I_CIRC:
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_A_BR:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
@@ -4411,7 +4411,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_ST_A_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_B_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
@@ -4419,7 +4419,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_ST_B_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_D_BR:
CHECK_REG_PAIR(r1);
@@ -4434,7 +4434,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_DA_BR:
CHECK_REG_PAIR(r1);
@@ -4449,7 +4449,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_H_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
@@ -4457,7 +4457,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_ST_H_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_Q_BR:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
@@ -4467,7 +4467,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
case OPC2_32_BO_ST_Q_CIRC:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_W_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
@@ -4475,7 +4475,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_ST_W_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4619,8 +4619,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int r1, r2;
-
- TCGv temp, temp2, temp3;
+ TCGv temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
@@ -4629,7 +4628,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- temp3 = tcg_const_i32(off10);
+ t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
@@ -4642,7 +4641,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_A_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_B_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
@@ -4650,7 +4649,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_B_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_BU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
@@ -4658,7 +4657,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_BU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_D_BR:
CHECK_REG_PAIR(r1);
@@ -4673,7 +4672,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_DA_BR:
CHECK_REG_PAIR(r1);
@@ -4688,7 +4687,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_H_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
@@ -4696,7 +4695,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_H_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_HU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
@@ -4704,7 +4703,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_HU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_Q_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
@@ -4714,7 +4713,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
case OPC2_32_BO_LD_Q_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_W_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
@@ -4722,7 +4721,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_W_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4823,8 +4822,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int r1, r2;
-
- TCGv temp, temp2, temp3;
+ TCGv temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
@@ -4833,7 +4831,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- temp3 = tcg_const_i32(off10);
+ t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
@@ -4845,7 +4843,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LDMST_CIRC:
gen_ldmst(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_SWAP_W_BR:
gen_swap(ctx, r1, temp2);
@@ -4853,7 +4851,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_SWAP_W_CIRC:
gen_swap(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_CMPSWAP_W_BR:
gen_cmpswap(ctx, r1, temp2);
@@ -4861,7 +4859,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_CMPSWAP_W_CIRC:
gen_cmpswap(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_SWAPMSK_W_BR:
gen_swapmsk(ctx, r1, temp2);
@@ -4869,7 +4867,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_SWAPMSK_W_CIRC:
gen_swapmsk(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 64/91] target/tricore: Use setcondi instead of explicit allocation
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (62 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 63/91] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 65/91] target/tricore: Drop some temp initialization Richard Henderson
` (27 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
This removes the only use of temp.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 19cf4b6cc7..6b2065803f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3514,17 +3514,14 @@ static void decode_sr_accu(DisasContext *ctx)
{
uint32_t op2;
uint32_t r1;
- TCGv temp;
r1 = MASK_OP_SR_S1D(ctx->opcode);
op2 = MASK_OP_SR_OP2(ctx->opcode);
switch (op2) {
case OPC2_16_SR_RSUB:
- /* overflow only if r1 = -0x80000000 */
- temp = tcg_const_i32(-0x80000000);
- /* calc V bit */
- tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
+ /* calc V bit -- overflow only if r1 = -0x80000000 */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 65/91] target/tricore: Drop some temp initialization
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (63 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 64/91] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 66/91] target/tricore: Avoid tcg_const_i32 Richard Henderson
` (26 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
The temp variables here are always set afterward;
the initialization with a constant was discarded.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6b2065803f..4e3e648049 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6914,7 +6914,7 @@ static void decode_rrr1_maddq_h(DisasContext *ctx)
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
- temp = tcg_const_i32(n);
+ temp = tcg_temp_new();
temp2 = tcg_temp_new();
switch (op2) {
@@ -7396,7 +7396,7 @@ static void decode_rrr1_msubq_h(DisasContext *ctx)
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
- temp = tcg_const_i32(n);
+ temp = tcg_temp_new();
temp2 = tcg_temp_new();
switch (op2) {
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 66/91] target/tricore: Avoid tcg_const_i32
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (64 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 65/91] target/tricore: Drop some temp initialization Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 67/91] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
` (25 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 127 +++++++++++++++++++------------------
1 file changed, 64 insertions(+), 63 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4e3e648049..a3a5263a5d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -124,7 +124,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
/* Makros for generating helpers */
#define gen_helper_1arg(name, arg) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg); \
+ TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
gen_helper_##name(cpu_env, helper_tmp); \
} while (0)
@@ -513,7 +513,7 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_madd32_d(ret, r1, r2, temp);
}
@@ -579,7 +579,7 @@ static inline void
gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
@@ -587,7 +587,7 @@ static inline void
gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
@@ -1224,7 +1224,7 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_msub32_d(ret, r1, r2, temp);
}
@@ -1260,7 +1260,7 @@ static inline void
gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
@@ -1296,13 +1296,13 @@ static inline void
gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
{
- TCGv temp = tcg_const_i32(r2);
+ TCGv temp = tcg_constant_i32(r2);
gen_add_d(ret, r1, temp);
}
@@ -1332,7 +1332,7 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_add_CC(ret, r1, temp);
}
@@ -1364,7 +1364,7 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_addc_CC(ret, r1, temp);
}
@@ -1375,7 +1375,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
TCGv temp2 = tcg_temp_new();
TCGv result = tcg_temp_new();
TCGv mask = tcg_temp_new();
- TCGv t0 = tcg_const_i32(0);
+ TCGv t0 = tcg_constant_i32(0);
/* create mask for sticky bits */
tcg_gen_setcond_tl(cond, mask, r4, t0);
@@ -1404,7 +1404,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
TCGv r3, TCGv r4)
{
- TCGv temp = tcg_const_i32(r2);
+ TCGv temp = tcg_constant_i32(r2);
gen_cond_add(cond, r1, temp, r3, r4);
}
@@ -1492,7 +1492,7 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
TCGv temp2 = tcg_temp_new();
TCGv result = tcg_temp_new();
TCGv mask = tcg_temp_new();
- TCGv t0 = tcg_const_i32(0);
+ TCGv t0 = tcg_constant_i32(0);
/* create mask for sticky bits */
tcg_gen_setcond_tl(cond, mask, r4, t0);
@@ -1705,14 +1705,14 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
static inline void
gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv temp = tcg_constant_i32(n);
gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
}
static inline void
gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
- TCGv temp = tcg_const_i32(n);
+ TCGv temp = tcg_constant_i32(n);
gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
}
@@ -2149,13 +2149,13 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_absdif(ret, r1, temp);
}
static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
}
@@ -2181,7 +2181,7 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_mul_i32s(ret, r1, temp);
}
@@ -2202,7 +2202,7 @@ static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_mul_i64s(ret_low, ret_high, r1, temp);
}
@@ -2223,31 +2223,32 @@ static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_mul_i64u(ret_low, ret_high, r1, temp);
}
static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_mul_ssov(ret, cpu_env, r1, temp);
}
static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_mul_suov(ret, cpu_env, r1, temp);
}
+
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
}
static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
}
@@ -2370,7 +2371,7 @@ static inline void
gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
@@ -2388,19 +2389,19 @@ static inline void
gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
}
static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
}
@@ -2418,7 +2419,7 @@ static inline void
gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
@@ -2436,7 +2437,7 @@ static inline void
gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
@@ -2507,8 +2508,8 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
/* clear PSW.V */
tcg_gen_movi_tl(cpu_PSW_V, 0);
} else if (shift_count > 0) {
- TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
- TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
+ TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count);
+ TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count);
/* calc carry */
msk_start = 32 - shift_count;
@@ -2546,7 +2547,7 @@ static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_shas(ret, r1, temp);
}
@@ -2588,7 +2589,7 @@ static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_sh_cond(cond, ret, r1, temp);
}
@@ -2599,13 +2600,13 @@ static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_add_ssov(ret, cpu_env, r1, temp);
}
static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_helper_add_suov(ret, cpu_env, r1, temp);
}
@@ -2675,7 +2676,7 @@ static inline void
gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
void(*op)(TCGv, TCGv, TCGv))
{
- TCGv temp = tcg_const_i32(con);
+ TCGv temp = tcg_constant_i32(con);
gen_accumulating_cond(cond, ret, r1, temp, op);
}
@@ -2842,8 +2843,8 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void generate_trap(DisasContext *ctx, int class, int tin)
{
- TCGv_i32 classtemp = tcg_const_i32(class);
- TCGv_i32 tintemp = tcg_const_i32(tin);
+ TCGv_i32 classtemp = tcg_constant_i32(class);
+ TCGv_i32 tintemp = tcg_constant_i32(tin);
gen_save_pc(ctx->base.pc_next);
gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
@@ -2865,7 +2866,7 @@ static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
int r2, int16_t address)
{
- TCGv temp = tcg_const_i32(r2);
+ TCGv temp = tcg_constant_i32(r2);
gen_branch_cond(ctx, cond, r1, temp, address);
}
@@ -3194,14 +3195,14 @@ static void decode_src_opc(DisasContext *ctx, int op1)
cpu_gpr_d[15]);
break;
case OPC1_16_SRC_CMOV:
- temp = tcg_const_tl(0);
- temp2 = tcg_const_tl(const4);
+ temp = tcg_constant_tl(0);
+ temp2 = tcg_constant_tl(const4);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
break;
case OPC1_16_SRC_CMOVN:
- temp = tcg_const_tl(0);
- temp2 = tcg_const_tl(const4);
+ temp = tcg_constant_tl(0);
+ temp2 = tcg_constant_tl(const4);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
break;
@@ -3267,12 +3268,12 @@ static void decode_srr_opc(DisasContext *ctx, int op1)
tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_CMOV:
- temp = tcg_const_tl(0);
+ temp = tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
break;
case OPC1_16_SRR_CMOVN:
- temp = tcg_const_tl(0);
+ temp = tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
break;
@@ -3797,7 +3798,7 @@ static void decode_abs_ldw(DisasContext *ctx)
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_LD_A:
@@ -3830,7 +3831,7 @@ static void decode_abs_ldb(DisasContext *ctx)
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_LD_B:
@@ -3861,7 +3862,7 @@ static void decode_abs_ldst_swap(DisasContext *ctx)
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_LDMST:
@@ -3912,7 +3913,7 @@ static void decode_abs_store(DisasContext *ctx)
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_ST_A:
@@ -3945,7 +3946,7 @@ static void decode_abs_storeb_h(DisasContext *ctx)
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_ST_B:
@@ -5303,7 +5304,7 @@ static void decode_rcpw_insert(DisasContext *ctx)
case OPC2_32_RCPW_INSERT:
/* if pos + width > 32 undefined result */
if (pos + width <= 32) {
- temp = tcg_const_i32(const4);
+ temp = tcg_constant_i32(const4);
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
}
break;
@@ -5379,14 +5380,14 @@ static void decode_rcr_cond_select(DisasContext *ctx)
cpu_gpr_d[r3]);
break;
case OPC2_32_RCR_SEL:
- temp = tcg_const_i32(0);
- temp2 = tcg_const_i32(const9);
+ temp = tcg_constant_i32(0);
+ temp2 = tcg_constant_i32(const9);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
break;
case OPC2_32_RCR_SELN:
- temp = tcg_const_i32(0);
- temp2 = tcg_const_i32(const9);
+ temp = tcg_constant_i32(0);
+ temp2 = tcg_constant_i32(const9);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
break;
@@ -6263,7 +6264,7 @@ static void decode_rr1_mul(DisasContext *ctx)
r1 = MASK_OP_RR1_S1(ctx->opcode);
r2 = MASK_OP_RR1_S2(ctx->opcode);
r3 = MASK_OP_RR1_D(ctx->opcode);
- n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
+ n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode));
op2 = MASK_OP_RR1_OP2(ctx->opcode);
switch (op2) {
@@ -6557,12 +6558,12 @@ static void decode_rrr_cond_select(DisasContext *ctx)
cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_SEL:
- temp = tcg_const_i32(0);
+ temp = tcg_constant_i32(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_SELN:
- temp = tcg_const_i32(0);
+ temp = tcg_constant_i32(0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
@@ -7964,7 +7965,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
case OPC1_32_ABS_STOREQ:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
temp2 = tcg_temp_new();
tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
@@ -7973,7 +7974,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
case OPC1_32_ABS_LD_Q:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
@@ -7989,7 +7990,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
b = MASK_OP_ABSB_B(ctx->opcode);
bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
- temp = tcg_const_i32(EA_ABS_FORMAT(address));
+ temp = tcg_constant_i32(EA_ABS_FORMAT(address));
temp2 = tcg_temp_new();
tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
@@ -8116,7 +8117,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
r2 = MASK_OP_RCRR_S3(ctx->opcode);
r3 = MASK_OP_RCRR_D(ctx->opcode);
const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
- temp = tcg_const_i32(const16);
+ temp = tcg_constant_i32(const16);
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 67/91] tcg: Replace tcg_const_i64 in tcg-op.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (65 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 66/91] target/tricore: Avoid tcg_const_i32 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 68/91] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
` (24 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
These three instances got missed in previous conversion.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 1a039a292c..ddab20a6a6 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1563,9 +1563,7 @@ void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} else if (is_power_of_2(arg2)) {
tcg_gen_shli_i64(ret, arg1, ctz64(arg2));
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_mul_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_mul_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -1962,9 +1960,7 @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
tcg_temp_free_i32(t);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_clz_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -2016,9 +2012,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_gen_ctpop_i64(ret, t);
tcg_temp_free_i64(t);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_ctz_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_ctz_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 68/91] target/arm: Use rmode >= 0 for need_rmode
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (66 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 67/91] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 69/91] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
` (23 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Initialize rmode to -1 instead of keeping two variables.
This is already used elsewhere in translate-a64.c.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 34 ++++++----------------------------
1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2c2ea45b47..bef66086a2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -12133,7 +12133,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool need_fpstatus = false;
- bool need_rmode = false;
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
@@ -12283,7 +12282,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
need_fpstatus = true;
- need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -12293,7 +12291,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5c: /* FCVTAU */
case 0x1c: /* FCVTAS */
need_fpstatus = true;
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -12352,7 +12349,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
- need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
/* fall through */
case 0x59: /* FRINTX */
@@ -12364,7 +12360,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
case 0x58: /* FRINTA */
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
need_fpstatus = true;
if (size == 3 && !is_q) {
@@ -12380,7 +12375,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
case 0x1e: /* FRINT32Z */
case 0x1f: /* FRINT64Z */
- need_rmode = true;
rmode = FPROUNDING_ZERO;
/* fall through */
case 0x5e: /* FRINT32X */
@@ -12406,12 +12400,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
- if (need_fpstatus || need_rmode) {
+ if (need_fpstatus || rmode >= 0) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
} else {
tcg_fpstatus = NULL;
}
- if (need_rmode) {
+ if (rmode >= 0) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
} else {
@@ -12595,7 +12589,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
clear_vec_high(s, is_q, rd);
- if (need_rmode) {
+ if (tcg_rmode) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
}
}
@@ -12625,9 +12619,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
int pass;
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr tcg_fpstatus = NULL;
- bool need_rmode = false;
bool need_fpst = true;
- int rmode;
+ int rmode = -1;
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
@@ -12676,27 +12669,22 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3f: /* FRECPX */
break;
case 0x18: /* FRINTN */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x19: /* FRINTM */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x38: /* FRINTP */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_POSINF;
break;
case 0x39: /* FRINTZ */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_ZERO;
break;
case 0x58: /* FRINTA */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEAWAY;
break;
@@ -12706,43 +12694,33 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
/* current rounding mode */
break;
case 0x1a: /* FCVTNS */
- need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x1b: /* FCVTMS */
- need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x1c: /* FCVTAS */
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x3a: /* FCVTPS */
- need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x3b: /* FCVTZS */
- need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x5a: /* FCVTNU */
- need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x5b: /* FCVTMU */
- need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x5c: /* FCVTAU */
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x7a: /* FCVTPU */
- need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x7b: /* FCVTZU */
- need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x2f: /* FABS */
@@ -12775,11 +12753,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
return;
}
- if (need_rmode || need_fpst) {
+ if (rmode >= 0 || need_fpst) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16);
}
- if (need_rmode) {
+ if (rmode >= 0) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 69/91] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (67 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 68/91] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 70/91] target/arm: Improve arm_rmode_to_sf Richard Henderson
` (22 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
While this enumerator has been present since the first commit,
it isn't ever used. The first actual use of round-to-odd came
with SVE, which currently uses float_round_to_odd instead of
the arm-specific enumerator.
Amusingly, the comment about unhandled TIEAWAY has been
out of date since the initial commit of translate-a64.c.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vfp_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 24e3d820a5..90cc324f71 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1111,10 +1111,8 @@ int arm_rmode_to_sf(int rmode)
rmode = float_round_ties_away;
break;
case FPROUNDING_ODD:
- /* FIXME: add support for TIEAWAY and ODD */
- qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
- rmode);
- /* fall through for now */
+ rmode = float_round_to_odd;
+ break;
case FPROUNDING_TIEEVEN:
default:
rmode = float_round_nearest_even;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 70/91] target/arm: Improve arm_rmode_to_sf
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (68 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 69/91] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 71/91] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
` (21 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Use proper enumeration types for input and output.
Use a const array to perform the mapping, with an
assert that the input is valid.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 12 +++++++++---
target/arm/tcg/translate-mve.c | 2 +-
target/arm/vfp_helper.c | 33 ++++++++-------------------------
3 files changed, 18 insertions(+), 29 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b1ef05963f..673519a24a 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -193,16 +193,22 @@ void arm_restore_state_to_opc(CPUState *cs,
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
#endif /* CONFIG_TCG */
-enum arm_fprounding {
+typedef enum ARMFPRounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
FPROUNDING_NEGINF,
FPROUNDING_ZERO,
FPROUNDING_TIEAWAY,
FPROUNDING_ODD
-};
+} ARMFPRounding;
-int arm_rmode_to_sf(int rmode);
+extern const FloatRoundMode arm_rmode_to_sf_map[6];
+
+static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
+{
+ assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map));
+ return arm_rmode_to_sf_map[rmode];
+}
static inline void aarch64_save_sp(CPUARMState *env, int el)
{
diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c
index 798b4fddfe..9744bf3de0 100644
--- a/target/arm/tcg/translate-mve.c
+++ b/target/arm/tcg/translate-mve.c
@@ -588,7 +588,7 @@ DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)
static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
- enum arm_fprounding rmode, bool u)
+ ARMFPRounding rmode, bool u)
{
/*
* Handle VCVT fp to int with specified rounding mode.
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 90cc324f71..36906db8e0 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1104,31 +1104,14 @@ float64 HELPER(rintd)(float64 x, void *fp_status)
}
/* Convert ARM rounding mode to softfloat */
-int arm_rmode_to_sf(int rmode)
-{
- switch (rmode) {
- case FPROUNDING_TIEAWAY:
- rmode = float_round_ties_away;
- break;
- case FPROUNDING_ODD:
- rmode = float_round_to_odd;
- break;
- case FPROUNDING_TIEEVEN:
- default:
- rmode = float_round_nearest_even;
- break;
- case FPROUNDING_POSINF:
- rmode = float_round_up;
- break;
- case FPROUNDING_NEGINF:
- rmode = float_round_down;
- break;
- case FPROUNDING_ZERO:
- rmode = float_round_to_zero;
- break;
- }
- return rmode;
-}
+const FloatRoundMode arm_rmode_to_sf_map[] = {
+ [FPROUNDING_TIEEVEN] = float_round_nearest_even,
+ [FPROUNDING_POSINF] = float_round_up,
+ [FPROUNDING_NEGINF] = float_round_down,
+ [FPROUNDING_ZERO] = float_round_to_zero,
+ [FPROUNDING_TIEAWAY] = float_round_ties_away,
+ [FPROUNDING_ODD] = float_round_to_odd,
+};
/*
* Implement float64 to int32_t conversion without saturation;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 71/91] target/arm: Consistently use ARMFPRounding during translation
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (69 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 70/91] target/arm: Improve arm_rmode_to_sf Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 72/91] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
` (20 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
In preparation for extracting new helpers, ensure that
the rounding mode is represented as ARMFPRounding and
not FloatRoundMode.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 16 ++++++++--------
target/arm/tcg/translate-sve.c | 18 +++++++++---------
target/arm/tcg/translate-vfp.c | 6 +++---
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bef66086a2..210899ff79 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6202,7 +6202,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
- rmode = arm_rmode_to_sf(opcode & 7);
+ rmode = opcode & 7;
gen_fpst = gen_helper_rints;
break;
case 0xe: /* FRINTX */
@@ -6212,14 +6212,14 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rints;
break;
case 0x10: /* FRINT32Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_s;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_s;
break;
case 0x12: /* FRINT64Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_s;
break;
case 0x13: /* FRINT64X */
@@ -6231,7 +6231,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -6275,7 +6275,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
- rmode = arm_rmode_to_sf(opcode & 7);
+ rmode = opcode & 7;
gen_fpst = gen_helper_rintd;
break;
case 0xe: /* FRINTX */
@@ -6285,14 +6285,14 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rintd;
break;
case 0x10: /* FRINT32Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_d;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_d;
break;
case 0x12: /* FRINT64Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_d;
break;
case 0x13: /* FRINT64X */
@@ -6304,7 +6304,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 5bf80b22d7..3c65dd1ff2 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4082,7 +4082,7 @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
- int mode, gen_helper_gvec_3_ptr *fn)
+ ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
{
unsigned vsz;
TCGv_i32 tmode;
@@ -4096,7 +4096,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- tmode = tcg_const_i32(mode);
+ tmode = tcg_const_i32(arm_rmode_to_sf(mode));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tmode, tmode, status);
@@ -4111,15 +4111,15 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
- float_round_nearest_even, frint_fns[a->esz])
+ FPROUNDING_TIEEVEN, frint_fns[a->esz])
TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
- float_round_up, frint_fns[a->esz])
+ FPROUNDING_POSINF, frint_fns[a->esz])
TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
- float_round_down, frint_fns[a->esz])
+ FPROUNDING_NEGINF, frint_fns[a->esz])
TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
- float_round_to_zero, frint_fns[a->esz])
+ FPROUNDING_ZERO, frint_fns[a->esz])
TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
- float_round_ties_away, frint_fns[a->esz])
+ FPROUNDING_TIEAWAY, frint_fns[a->esz])
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
NULL, gen_helper_sve_frecpx_h,
@@ -7145,9 +7145,9 @@ TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
- float_round_to_odd, gen_helper_sve_fcvt_ds)
+ FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
- float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
+ FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds)
static gen_helper_gvec_3_ptr * const flogb_fns[] = {
NULL, gen_helper_flogb_h,
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index 757a2bf7d9..e7acfb3338 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -2783,7 +2783,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -2808,7 +2808,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -2842,7 +2842,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 72/91] target/arm: Create gen_set_rmode, gen_restore_rmode
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (70 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 71/91] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 73/91] target/arm: Improve trans_BFCI Richard Henderson
` (19 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Split out common subroutines for handing rounding mode
changes during translation. Use tcg_constant_i32 and
tcg_temp_new_i32 instead of tcg_const_i32.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.h | 17 ++++++++++++
target/arm/tcg/translate-a64.c | 47 ++++++++++++++--------------------
target/arm/tcg/translate-sve.c | 6 ++---
target/arm/tcg/translate-vfp.c | 26 ++++++++-----------
4 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 20f3ca7aca..f02d4685b4 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -616,6 +616,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
return ret;
}
+/*
+ * Set and reset rounding mode around another operation.
+ */
+static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
+{
+ TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
+ TCGv_i32 old = tcg_temp_new_i32();
+
+ gen_helper_set_rmode(old, new, fpst);
+ return old;
+}
+
+static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
+{
+ gen_helper_set_rmode(old, old, fpst);
+}
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 210899ff79..989c958de6 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6146,13 +6146,12 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
{
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+ TCGv_i32 tcg_rmode;
+
fpst = fpstatus_ptr(FPST_FPCR_F16);
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(opcode & 7, fpst);
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
break;
}
case 0xe: /* FRINTX */
@@ -6231,10 +6230,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6304,10 +6302,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6944,9 +6941,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
rmode = FPROUNDING_TIEAWAY;
}
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
switch (type) {
case 1: /* float64 */
@@ -7023,7 +7018,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
g_assert_not_reached();
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -8771,9 +8766,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
assert(!(is_scalar && is_q));
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus);
fracbits = (16 << size) - immhb;
tcg_shift = tcg_constant_i32(fracbits);
@@ -8831,7 +8825,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
}
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
/* AdvSIMD scalar shift by immediate
@@ -10219,12 +10213,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
- tcg_rmode = NULL;
tcg_fpstatus = NULL;
+ tcg_rmode = NULL;
}
if (size == 3) {
@@ -10276,7 +10269,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12406,8 +12399,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_fpstatus = NULL;
}
if (rmode >= 0) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
}
@@ -12590,7 +12582,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
clear_vec_high(s, is_q, rd);
if (tcg_rmode) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12758,8 +12750,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (rmode >= 0) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
}
if (is_scalar) {
@@ -12859,7 +12850,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (tcg_rmode) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 3c65dd1ff2..3ca60fb36b 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4096,17 +4096,15 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- tmode = tcg_const_i32(arm_rmode_to_sf(mode));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
-
- gen_helper_set_rmode(tmode, tmode, status);
+ tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);
- gen_helper_set_rmode(tmode, tmode, status);
+ gen_restore_rmode(tmode, status);
return true;
}
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index e7acfb3338..dd782aacf4 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
fpst = fpstatus_ptr(FPST_FPCR);
}
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_op;
@@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
vfp_store_reg32(tcg_res, rd);
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
tcg_shift = tcg_constant_i32(0);
-
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_double, tcg_res;
@@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
vfp_store_reg32(tcg_res, rd);
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 73/91] target/arm: Improve trans_BFCI
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (71 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 72/91] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 74/91] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
` (18 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b70b628000..4451aea09c 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
- TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
+ TCGv_i32 t_in, t_rd;
int width;
if (!ENABLE_ARCH_6T2) {
@@ -7277,16 +7277,13 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
- tmp = tcg_const_i32(0);
+ t_in = tcg_constant_i32(0);
} else {
/* BFI */
- tmp = load_reg(s, a->rn);
+ t_in = load_reg(s, a->rn);
}
- if (width != 32) {
- TCGv_i32 tmp2 = load_reg(s, a->rd);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
- }
- store_reg(s, a->rd, tmp);
+ t_rd = load_reg(s, a->rd);
+ tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 74/91] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (72 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 73/91] target/arm: Improve trans_BFCI Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
` (17 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
This hides the implicit initialization of a variable.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-sve.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 3ca60fb36b..92ab290106 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4206,8 +4206,9 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
- TCGv_ptr tp, i = tcg_const_ptr(0);
+ TCGv_ptr tp, i = tcg_temp_new_ptr();
+ tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@@ -4284,8 +4285,9 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
- TCGv_ptr tp, i = tcg_const_ptr(0);
+ TCGv_ptr tp, i = tcg_temp_new_ptr();
+ tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (73 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 74/91] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
` (16 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All uses are in the context of an accumulator conditionally
having a zero input. Split the rda variable to rda_{i,o},
and set rda_i to tcg_constant_foo(0) when required.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-mve.c | 54 ++++++++++++++++++----------------
1 file changed, 29 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c
index 9744bf3de0..31fb2110f1 100644
--- a/target/arm/tcg/translate-mve.c
+++ b/target/arm/tcg/translate-mve.c
@@ -1150,7 +1150,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenLongDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
- TCGv_i64 rda;
+ TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s) ||
@@ -1177,21 +1177,22 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current rda value, not 0.
*/
+ rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
- rda = tcg_temp_new_i64();
+ rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
- tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+ tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
- rda = tcg_const_i64(0);
+ rda_i = tcg_constant_i64(0);
}
- fn(rda, cpu_env, qn, qm, rda);
+ fn(rda_o, cpu_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(rdalo, rda);
- tcg_gen_extrh_i64_i32(rdahi, rda);
+ tcg_gen_extrl_i64_i32(rdalo, rda_o);
+ tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
@@ -1258,7 +1259,7 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
- TCGv_i32 rda;
+ TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
!mve_check_qreg_bank(s, a->qn) ||
@@ -1278,13 +1279,14 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
* beat must start with the current rda value, not 0.
*/
if (a->a || mve_skip_first_beat(s)) {
- rda = load_reg(s, a->rda);
+ rda_o = rda_i = load_reg(s, a->rda);
} else {
- rda = tcg_const_i32(0);
+ rda_i = tcg_constant_i32(0);
+ rda_o = tcg_temp_new_i32();
}
- fn(rda, cpu_env, qn, qm, rda);
- store_reg(s, a->rda, rda);
+ fn(rda_o, cpu_env, qn, qm, rda_i);
+ store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@@ -1396,7 +1398,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
{ NULL, NULL }
};
TCGv_ptr qm;
- TCGv_i32 rda;
+ TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
a->size == 3) {
@@ -1413,15 +1415,16 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
*/
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from Rda */
- rda = load_reg(s, a->rda);
+ rda_o = rda_i = load_reg(s, a->rda);
} else {
/* Accumulate starting at zero */
- rda = tcg_const_i32(0);
+ rda_i = tcg_constant_i32(0);
+ rda_o = tcg_temp_new_i32();
}
qm = mve_qreg_ptr(a->qm);
- fns[a->size][a->u](rda, cpu_env, qm, rda);
- store_reg(s, a->rda, rda);
+ fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
+ store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@@ -1436,7 +1439,7 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* No need to check Qm's bank: it is only 3 bits in decode.
*/
TCGv_ptr qm;
- TCGv_i64 rda;
+ TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s)) {
@@ -1458,28 +1461,29 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current value of RdaHi:RdaLo, not zero.
*/
+ rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from RdaHi:RdaLo */
- rda = tcg_temp_new_i64();
+ rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
- tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+ tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
/* Accumulate starting at zero */
- rda = tcg_const_i64(0);
+ rda_i = tcg_constant_i64(0);
}
qm = mve_qreg_ptr(a->qm);
if (a->u) {
- gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
+ gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
} else {
- gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
+ gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
}
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(rdalo, rda);
- tcg_gen_extrh_i64_i32(rdahi, rda);
+ tcg_gen_extrl_i64_i32(rdalo, rda_o);
+ tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (74 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
` (15 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
It is easy enough to use mov instead of or-with-zero and relying
on the optimizer to fold away the or. Use an array for the output,
rather than separate tcg_res{l,h} variables.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 41 +++++++++++++++++-----------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 989c958de6..2ad7c48901 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7442,10 +7442,10 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
bool part = extract32(insn, 14, 1);
bool is_q = extract32(insn, 30, 1);
int esize = 8 << size;
- int i, ofs;
+ int i;
int datasize = is_q ? 128 : 64;
int elements = datasize / esize;
- TCGv_i64 tcg_res, tcg_resl, tcg_resh;
+ TCGv_i64 tcg_res[2], tcg_ele;
if (opcode == 0 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@@ -7456,37 +7456,39 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
return;
}
- tcg_resl = tcg_const_i64(0);
- tcg_resh = is_q ? tcg_const_i64(0) : NULL;
- tcg_res = tcg_temp_new_i64();
+ tcg_res[0] = tcg_temp_new_i64();
+ tcg_res[1] = is_q ? tcg_temp_new_i64() : NULL;
+ tcg_ele = tcg_temp_new_i64();
for (i = 0; i < elements; i++) {
+ int o, w;
+
switch (opcode) {
case 1: /* UZP1/2 */
{
int midpoint = elements / 2;
if (i < midpoint) {
- read_vec_element(s, tcg_res, rn, 2 * i + part, size);
+ read_vec_element(s, tcg_ele, rn, 2 * i + part, size);
} else {
- read_vec_element(s, tcg_res, rm,
+ read_vec_element(s, tcg_ele, rm,
2 * (i - midpoint) + part, size);
}
break;
}
case 2: /* TRN1/2 */
if (i & 1) {
- read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
+ read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size);
} else {
- read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
+ read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size);
}
break;
case 3: /* ZIP1/2 */
{
int base = part * elements / 2;
if (i & 1) {
- read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
+ read_vec_element(s, tcg_ele, rm, base + (i >> 1), size);
} else {
- read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
+ read_vec_element(s, tcg_ele, rn, base + (i >> 1), size);
}
break;
}
@@ -7494,19 +7496,18 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
g_assert_not_reached();
}
- ofs = i * esize;
- if (ofs < 64) {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
- tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
+ w = (i * esize) / 64;
+ o = (i * esize) % 64;
+ if (o == 0) {
+ tcg_gen_mov_i64(tcg_res[w], tcg_ele);
} else {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
- tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
+ tcg_gen_shli_i64(tcg_ele, tcg_ele, o);
+ tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele);
}
}
- write_vec_element(s, tcg_resl, rd, 0, MO_64);
- if (is_q) {
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
+ for (i = 0; i <= is_q; ++i) {
+ write_vec_element(s, tcg_res[i], rd, i, MO_64);
}
clear_vec_high(s, is_q, rd);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (75 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2024-01-23 15:09 ` Peter Maydell
2023-03-09 20:05 ` [PULL v2 78/91] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
` (14 subsequent siblings)
91 siblings, 1 reply; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
It is easy enough to use mov instead of or-with-zero
and relying on the optimizer to fold away the or.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2ad7c48901..082a8b82dd 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8459,7 +8459,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
tcg_rn = tcg_temp_new_i64();
tcg_rd = tcg_temp_new_i64();
tcg_rd_narrowed = tcg_temp_new_i32();
- tcg_final = tcg_const_i64(0);
+ tcg_final = tcg_temp_new_i64();
if (round) {
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
@@ -8473,7 +8473,11 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
false, is_u_shift, size+1, shift);
narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
- tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
+ if (i == 0) {
+ tcg_gen_mov_i64(tcg_final, tcg_rd);
+ } else {
+ tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
+ }
}
if (!is_q) {
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
2023-03-09 20:05 ` [PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
@ 2024-01-23 15:09 ` Peter Maydell
0 siblings, 0 replies; 94+ messages in thread
From: Peter Maydell @ 2024-01-23 15:09 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Philippe Mathieu-Daudé
On Thu, 9 Mar 2023 at 20:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> It is easy enough to use mov instead of or-with-zero
> and relying on the optimizer to fold away the or.
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 2ad7c48901..082a8b82dd 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -8459,7 +8459,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
> tcg_rn = tcg_temp_new_i64();
> tcg_rd = tcg_temp_new_i64();
> tcg_rd_narrowed = tcg_temp_new_i32();
> - tcg_final = tcg_const_i64(0);
> + tcg_final = tcg_temp_new_i64();
>
> if (round) {
> tcg_round = tcg_constant_i64(1ULL << (shift - 1));
> @@ -8473,7 +8473,11 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
> false, is_u_shift, size+1, shift);
> narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
> tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
> - tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
> + if (i == 0) {
> + tcg_gen_mov_i64(tcg_final, tcg_rd);
> + } else {
> + tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
> + }
So, it turns out that this causes a regression:
https://gitlab.com/qemu-project/qemu/-/issues/2089
The change here is fine for the vector case, because when
we loop round the subsequent deposit ops will overwrite
the bits of tcg_final above the initial element, whatever
they happen to be in tcg_rd. However, for the scalar case
we only execute this loop once, and so after this change
instead of the high bits of the result being 0, we leave
them as whatever they were in tcg_rd. If the narrow is a
signed version and the result was negative, those high bits
will now be 1 instead of the 0 they should be.
Using
tcg_gen_extract_i64(tcg_final, tcg_rd, 0, esize);
instead of the tcg_gen_mov_i64() should fix this.
I'll send a patch later this afternoon.
thanks
-- PMM
^ permalink raw reply [flat|nested] 94+ messages in thread
* [PULL v2 78/91] target/arm: Avoid tcg_const_ptr in handle_rev
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (76 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 79/91] target/m68k: Use tcg_constant_i32 in gen_ea_mode Richard Henderson
` (13 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Here it is not trivial to notice first initialization, so explicitly
zero the temps. Use an array for the output, rather than separate
tcg_rd/tcg_rd_hi variables.
Fixes a bug by adding a missing clear_vec_high.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 082a8b82dd..dff391bfe2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -12003,22 +12003,26 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
int esize = 8 << size;
int elements = dsize / esize;
TCGv_i64 tcg_rn = tcg_temp_new_i64();
- TCGv_i64 tcg_rd = tcg_const_i64(0);
- TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
+ TCGv_i64 tcg_rd[2];
+
+ for (i = 0; i < 2; i++) {
+ tcg_rd[i] = tcg_temp_new_i64();
+ tcg_gen_movi_i64(tcg_rd[i], 0);
+ }
for (i = 0; i < elements; i++) {
int e_rev = (i & 0xf) ^ revmask;
- int off = e_rev * esize;
+ int w = (e_rev * esize) / 64;
+ int o = (e_rev * esize) % 64;
+
read_vec_element(s, tcg_rn, rn, i, size);
- if (off >= 64) {
- tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
- tcg_rn, off - 64, esize);
- } else {
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
- }
+ tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
}
- write_vec_element(s, tcg_rd, rd, 0, MO_64);
- write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
+
+ for (i = 0; i < 2; i++) {
+ write_vec_element(s, tcg_rd[i], rd, i, MO_64);
+ }
+ clear_vec_high(s, true, rd);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 79/91] target/m68k: Use tcg_constant_i32 in gen_ea_mode
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (77 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 78/91] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
` (12 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Return a constant for an immediate input.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 44c3ac0bc3..422f4652f1 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -916,7 +916,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
default:
g_assert_not_reached();
}
- return tcg_const_i32(offset);
+ return tcg_constant_i32(offset);
default:
return NULL_QREG;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (78 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 79/91] target/m68k: Use tcg_constant_i32 in gen_ea_mode Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
` (11 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
Compute both partial results separately and accumulate
at the end, instead of accumulating in the middle.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 7af6d7217d..ca27c11d87 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2236,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
{
- TCGv_i64 rt, vrb, mask;
- rt = tcg_const_i64(0);
- vrb = tcg_temp_new_i64();
+ TCGv_i64 r[2], mask;
+
+ r[0] = tcg_temp_new_i64();
+ r[1] = tcg_temp_new_i64();
mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
for (int i = 0; i < 2; i++) {
- get_avr64(vrb, a->vrb, i);
+ get_avr64(r[i], a->vrb, i);
if (a->mp) {
- tcg_gen_and_i64(vrb, mask, vrb);
+ tcg_gen_and_i64(r[i], mask, r[i]);
} else {
- tcg_gen_andc_i64(vrb, mask, vrb);
+ tcg_gen_andc_i64(r[i], mask, r[i]);
}
- tcg_gen_ctpop_i64(vrb, vrb);
- tcg_gen_add_i64(rt, rt, vrb);
+ tcg_gen_ctpop_i64(r[i], r[i]);
}
- tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
- tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
+ tcg_gen_add_i64(r[0], r[0], r[1]);
+ tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece);
+ tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (79 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 82/91] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
` (10 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vmx-impl.c.inc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index ca27c11d87..112233b541 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1624,7 +1624,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
- uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
+ uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb, uimm); \
@@ -1965,7 +1965,7 @@ static void gen_vsldoi(DisasContext *ctx)
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
- sh = tcg_const_i32(VSH(ctx->opcode));
+ sh = tcg_constant_i32(VSH(ctx->opcode));
gen_helper_vsldoi(rd, ra, rb, sh);
}
@@ -2575,7 +2575,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
- ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+ ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
}
@@ -2594,7 +2594,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
- ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+ ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, rb, ps); \
}
@@ -2726,7 +2726,7 @@ static void gen_##op(DisasContext *ctx) \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- st_six = tcg_const_i32(rB(ctx->opcode)); \
+ st_six = tcg_constant_i32(rB(ctx->opcode)); \
gen_helper_##op(rd, ra, st_six); \
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 82/91] target/ppc: Avoid tcg_const_* in xxeval
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (80 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
` (9 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
Initialize a new temp instead of tcg_const_*.
Fix a pasto in a comment.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vsx-impl.c.inc | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 6e63403727..9916784e64 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2449,7 +2449,8 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
TCGv_i64 conj, disj;
conj = tcg_temp_new_i64();
- disj = tcg_const_i64(0);
+ disj = tcg_temp_new_i64();
+ tcg_gen_movi_i64(disj, 0);
/* Iterate over set bits from the least to the most significant bit */
while (imm) {
@@ -2492,8 +2493,9 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
int bit;
TCGv_vec disj, conj;
- disj = tcg_const_zeros_vec_matching(t);
conj = tcg_temp_new_vec_matching(t);
+ disj = tcg_temp_new_vec_matching(t);
+ tcg_gen_dupi_vec(vece, disj, 0);
/* Iterate over set bits from the least to the most significant bit */
while (imm) {
@@ -2546,7 +2548,7 @@ static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)
/* Equivalent functions that can be implemented with a single gen_gvec */
switch (a->imm) {
- case 0b00000000: /* true */
+ case 0b00000000: /* false */
set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (81 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 82/91] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
` (8 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9916784e64..0f5b0056f1 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
- TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
+ TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
- ro = tcg_const_i32(a->rc);
+ ro = tcg_constant_i32(a->rc);
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
@@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \
}
@@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xb); \
}
@@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
@@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xb); \
@@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(2047);
get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
@@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(32767);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(32767);
tcg_gen_extract_i64(exp, xbh, 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
@@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(2047);
tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (82 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 85/91] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
` (7 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/fp-impl.c.inc | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index d5d88e7d49..57d8437851 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
- crf = tcg_const_i32(crfD(ctx->opcode));
+ crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpo(cpu_env, t0, t1, crf);
@@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
- crf = tcg_const_i32(crfD(ctx->opcode));
+ crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpu(cpu_env, t0, t1, crf);
@@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx)
tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */
- tmask = tcg_const_i32(1 << nibble);
+ tmask = tcg_constant_i32(1 << nibble);
gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
}
@@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
- TCGv_i32 t0;
- t0 = tcg_const_i32(crb);
- gen_helper_fpscr_clrbit(cpu_env, t0);
+ gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
- TCGv_i32 t0;
- t0 = tcg_const_i32(crb);
- gen_helper_fpscr_setbit(cpu_env, t0);
+ gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx)
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
- if (l) {
- t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
+ if (!l) {
+ t0 = tcg_constant_i32(flm << (w * 8));
+ } else if (ctx->insns_flags2 & PPC2_ISA205) {
+ t0 = tcg_constant_i32(0xffff);
} else {
- t0 = tcg_const_i32(flm << (w * 8));
+ t0 = tcg_constant_i32(0xff);
}
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
@@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx)
return;
}
sh = (8 * w) + 7 - bf;
- t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
- t1 = tcg_const_i32(1 << sh);
+ t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
+ t1 = tcg_constant_i32(1 << sh);
gen_helper_store_fpscr(cpu_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 85/91] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (83 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 86/91] target/ppc: Rewrite trans_ADDG6S Richard Henderson
` (6 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/power8-pmu-regs.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 42f2cd04a1..d900e13cad 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -177,7 +177,7 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
{
- TCGv_i32 t_sprn = tcg_const_i32(sprn);
+ TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
@@ -210,7 +210,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t_sprn = tcg_const_i32(sprn);
+ TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 86/91] target/ppc: Rewrite trans_ADDG6S
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (84 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 85/91] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 87/91] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
` (5 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Daniel Henrique Barboza
Compute all carry bits in parallel instead of a loop.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/fixedpoint-impl.c.inc | 44 +++++++++++-----------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 20ea484c3d..02d86b77a8 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
{
- const uint64_t carry_bits = 0x1111111111111111ULL;
- TCGv t0, t1, carry, zero = tcg_constant_tl(0);
+ const target_ulong carry_bits = (target_ulong)-1 / 0xf;
+ TCGv in1, in2, carryl, carryh, tmp;
+ TCGv zero = tcg_constant_tl(0);
REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
- t0 = tcg_temp_new();
- t1 = tcg_const_tl(0);
- carry = tcg_const_tl(0);
+ in1 = cpu_gpr[a->ra];
+ in2 = cpu_gpr[a->rb];
+ tmp = tcg_temp_new();
+ carryl = tcg_temp_new();
+ carryh = tcg_temp_new();
- for (int i = 0; i < 16; i++) {
- tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
- tcg_gen_andi_tl(t0, t0, 0xf);
- tcg_gen_add_tl(t1, t1, t0);
+ /* Addition with carry. */
+ tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
+ /* Addition without carry. */
+ tcg_gen_xor_tl(tmp, in1, in2);
+ /* Difference between the two is carry in to each bit. */
+ tcg_gen_xor_tl(carryl, carryl, tmp);
- tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
- tcg_gen_andi_tl(t0, t0, 0xf);
- tcg_gen_add_tl(t1, t1, t0);
+ /*
+ * The carry-out that we're looking for is the carry-in to
+ * the next nibble. Shift the double-word down one nibble,
+ * which puts all of the bits back into one word.
+ */
+ tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
- tcg_gen_andi_tl(t1, t1, 0x10);
- tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
-
- tcg_gen_shli_tl(t0, t1, i * 4);
- tcg_gen_or_tl(carry, carry, t0);
- }
-
- tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
- tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
+ /* Invert, isolate the carry bits, and produce 6's. */
+ tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
+ tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 87/91] target/ppc: Fix gen_tlbsx_booke206
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (85 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 86/91] target/ppc: Rewrite trans_ADDG6S Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 88/91] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
` (4 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Daniel Henrique Barboza
Fix incorrect read from rD.
Avoid adding 0 when rA == 0.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index df324fc7ff..7ec940b7d8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5875,12 +5875,10 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
CHK_SV(ctx);
if (rA(ctx->opcode)) {
t0 = tcg_temp_new();
- tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
+ tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
} else {
- t0 = tcg_const_tl(0);
+ t0 = cpu_gpr[rB(ctx->opcode)];
}
-
- tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
gen_helper_booke206_tlbsx(cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 88/91] target/ppc: Avoid tcg_const_* in translate.c
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (86 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 87/91] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 89/91] target/tricore: Use min/max for saturate Richard Henderson
` (3 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 142 +++++++++++++++++++++--------------------
1 file changed, 72 insertions(+), 70 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 7ec940b7d8..9d05357d03 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -263,8 +263,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
* faulting instruction
*/
gen_update_nip(ctx, ctx->cia);
- t0 = tcg_const_i32(excp);
- t1 = tcg_const_i32(error);
+ t0 = tcg_constant_i32(excp);
+ t1 = tcg_constant_i32(error);
gen_helper_raise_exception_err(cpu_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -278,7 +278,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
* faulting instruction
*/
gen_update_nip(ctx, ctx->cia);
- t0 = tcg_const_i32(excp);
+ t0 = tcg_constant_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -289,7 +289,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
TCGv_i32 t0;
gen_update_nip(ctx, nip);
- t0 = tcg_const_i32(excp);
+ t0 = tcg_constant_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
static void spr_load_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
+ TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_load_dump_spr(cpu_env, t0);
#endif
}
@@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
static void spr_store_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
+ TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_store_dump_spr(cpu_env, t0);
#endif
}
@@ -672,25 +672,25 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
}
@@ -712,25 +712,25 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
}
@@ -1040,13 +1040,15 @@ void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(sprn);
+ TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
}
+
void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
}
+
void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
@@ -1080,9 +1082,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
int bit, int sprn, int cause)
{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
+ TCGv_i32 t1 = tcg_constant_i32(bit);
+ TCGv_i32 t2 = tcg_constant_i32(sprn);
+ TCGv_i32 t3 = tcg_constant_i32(cause);
gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
}
@@ -1090,9 +1092,9 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
int bit, int sprn, int cause)
{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
+ TCGv_i32 t1 = tcg_constant_i32(bit);
+ TCGv_i32 t2 = tcg_constant_i32(sprn);
+ TCGv_i32 t3 = tcg_constant_i32(cause);
gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
}
@@ -1388,7 +1390,7 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
{
- TCGv t0 = tcg_const_tl(arg1);
+ TCGv t0 = tcg_constant_tl(arg1);
gen_op_cmp(arg0, t0, s, crf);
}
@@ -1409,7 +1411,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
{
- TCGv t0 = tcg_const_tl(arg1);
+ TCGv t0 = tcg_constant_tl(arg1);
gen_op_cmp32(arg0, t0, s, crf);
}
@@ -1476,7 +1478,7 @@ static void gen_isel(DisasContext *ctx)
tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
tcg_gen_andi_tl(t0, t0, mask);
- zr = tcg_const_tl(0);
+ zr = tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
cpu_gpr[rB(ctx->opcode)]);
@@ -1568,7 +1570,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ca32, ca);
}
} else {
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
if (add_ca) {
tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
@@ -1609,7 +1611,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
add_ca, compute_ca, compute_ov) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
- TCGv t0 = tcg_const_tl(const_val); \
+ TCGv t0 = tcg_constant_tl(const_val); \
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], t0, \
ca, glue(ca, 32), \
@@ -1636,7 +1638,7 @@ GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
- TCGv c = tcg_const_tl(SIMM(ctx->opcode));
+ TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
}
@@ -1709,7 +1711,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
#define GEN_DIVE(name, hlpr, compute_ov) \
static void gen_##name(DisasContext *ctx) \
{ \
- TCGv_i32 t0 = tcg_const_i32(compute_ov); \
+ TCGv_i32 t0 = tcg_constant_i32(compute_ov); \
gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
@@ -1802,8 +1804,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_rem_i32(t3, t0, t1);
tcg_gen_ext_i32_tl(ret, t3);
} else {
- TCGv_i32 t2 = tcg_const_i32(1);
- TCGv_i32 t3 = tcg_const_i32(0);
+ TCGv_i32 t2 = tcg_constant_i32(1);
+ TCGv_i32 t3 = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
tcg_gen_remu_i32(t3, t0, t1);
tcg_gen_extu_i32_tl(ret, t3);
@@ -1842,8 +1844,8 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_rem_i64(ret, t0, t1);
} else {
- TCGv_i64 t2 = tcg_const_i64(1);
- TCGv_i64 t3 = tcg_const_i64(0);
+ TCGv_i64 t2 = tcg_constant_i64(1);
+ TCGv_i64 t3 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
tcg_gen_remu_i64(ret, t0, t1);
}
@@ -2038,7 +2040,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
} else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
- zero = tcg_const_tl(0);
+ zero = tcg_constant_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
@@ -2083,7 +2085,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
add_ca, compute_ca, compute_ov) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
- TCGv t0 = tcg_const_tl(const_val); \
+ TCGv t0 = tcg_constant_tl(const_val); \
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], t0, \
add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
@@ -2107,7 +2109,7 @@ GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
/* subfic */
static void gen_subfic(DisasContext *ctx)
{
- TCGv c = tcg_const_tl(SIMM(ctx->opcode));
+ TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
c, 0, 1, 0, 0);
}
@@ -2115,7 +2117,7 @@ static void gen_subfic(DisasContext *ctx)
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
{
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
zero, 0, 0, compute_ov, Rc(ctx->opcode));
}
@@ -2214,7 +2216,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
static void gen_pause(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(0);
+ TCGv_i32 t0 = tcg_constant_i32(0);
tcg_gen_st_i32(t0, cpu_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
@@ -3256,7 +3258,7 @@ static void gen_lmw(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
- t1 = tcg_const_i32(rD(ctx->opcode));
+ t1 = tcg_constant_i32(rD(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
gen_helper_lmw(cpu_env, t0, t1);
}
@@ -3273,7 +3275,7 @@ static void gen_stmw(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
- t1 = tcg_const_i32(rS(ctx->opcode));
+ t1 = tcg_constant_i32(rS(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
gen_helper_stmw(cpu_env, t0, t1);
}
@@ -3311,8 +3313,8 @@ static void gen_lswi(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_register(ctx, t0);
- t1 = tcg_const_i32(nb);
- t2 = tcg_const_i32(start);
+ t1 = tcg_constant_i32(nb);
+ t2 = tcg_constant_i32(start);
gen_helper_lsw(cpu_env, t0, t1, t2);
}
@@ -3329,9 +3331,9 @@ static void gen_lswx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- t1 = tcg_const_i32(rD(ctx->opcode));
- t2 = tcg_const_i32(rA(ctx->opcode));
- t3 = tcg_const_i32(rB(ctx->opcode));
+ t1 = tcg_constant_i32(rD(ctx->opcode));
+ t2 = tcg_constant_i32(rA(ctx->opcode));
+ t3 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_lswx(cpu_env, t0, t1, t2, t3);
}
@@ -3352,8 +3354,8 @@ static void gen_stswi(DisasContext *ctx)
if (nb == 0) {
nb = 32;
}
- t1 = tcg_const_i32(nb);
- t2 = tcg_const_i32(rS(ctx->opcode));
+ t1 = tcg_constant_i32(nb);
+ t2 = tcg_constant_i32(rS(ctx->opcode));
gen_helper_stsw(cpu_env, t0, t1, t2);
}
@@ -3373,7 +3375,7 @@ static void gen_stswx(DisasContext *ctx)
t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, cpu_xer);
tcg_gen_andi_i32(t1, t1, 0x7F);
- t2 = tcg_const_i32(rS(ctx->opcode));
+ t2 = tcg_constant_i32(rS(ctx->opcode));
gen_helper_stsw(cpu_env, t0, t1, t2);
}
@@ -3943,7 +3945,7 @@ static void gen_wait(DisasContext *ctx)
* to occur.
*/
if (wc == 0) {
- TCGv_i32 t0 = tcg_const_i32(1);
+ TCGv_i32 t0 = tcg_constant_i32(1);
tcg_gen_st_i32(t0, cpu_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
/* Stop translation, as the CPU is supposed to sleep from now */
@@ -3989,7 +3991,7 @@ static void gen_doze(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_DOZE);
+ t = tcg_constant_i32(PPC_PM_DOZE);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4004,7 +4006,7 @@ static void gen_nap(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_NAP);
+ t = tcg_constant_i32(PPC_PM_NAP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4019,7 +4021,7 @@ static void gen_stop(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_STOP);
+ t = tcg_constant_i32(PPC_PM_STOP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4034,7 +4036,7 @@ static void gen_sleep(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_SLEEP);
+ t = tcg_constant_i32(PPC_PM_SLEEP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4049,7 +4051,7 @@ static void gen_rvwinkle(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_RVWINKLE);
+ t = tcg_constant_i32(PPC_PM_RVWINKLE);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4506,7 +4508,7 @@ static void gen_tw(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
@@ -4520,8 +4522,8 @@ static void gen_twi(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_tl(SIMM(ctx->opcode));
- t1 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_tl(SIMM(ctx->opcode));
+ t1 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
@@ -4534,7 +4536,7 @@ static void gen_td(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
@@ -4548,8 +4550,8 @@ static void gen_tdi(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_tl(SIMM(ctx->opcode));
- t1 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_tl(SIMM(ctx->opcode));
+ t1 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
#endif
@@ -5026,7 +5028,7 @@ static void gen_dcbz(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new();
- tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
+ tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
}
@@ -5039,7 +5041,7 @@ static void gen_dcbzep(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new();
- tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
+ tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
}
@@ -5114,7 +5116,7 @@ static void gen_mfsr(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5143,7 +5145,7 @@ static void gen_mtsr(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5175,7 +5177,7 @@ static void gen_mfsr_64b(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5204,7 +5206,7 @@ static void gen_mtsr_64b(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5558,7 +5560,7 @@ static void gen_mfdcr(DisasContext *ctx)
TCGv dcrn;
CHK_SV(ctx);
- dcrn = tcg_const_tl(SPR(ctx->opcode));
+ dcrn = tcg_constant_tl(SPR(ctx->opcode));
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5572,7 +5574,7 @@ static void gen_mtdcr(DisasContext *ctx)
TCGv dcrn;
CHK_SV(ctx);
- dcrn = tcg_const_tl(SPR(ctx->opcode));
+ dcrn = tcg_constant_tl(SPR(ctx->opcode));
gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5793,7 +5795,7 @@ static void gen_tlbre_440(DisasContext *ctx)
case 1:
case 2:
{
- TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
+ TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
t0, cpu_gpr[rA(ctx->opcode)]);
}
@@ -5839,7 +5841,7 @@ static void gen_tlbwe_440(DisasContext *ctx)
case 1:
case 2:
{
- TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
+ TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
}
@@ -5981,7 +5983,7 @@ static void gen_wrteei(DisasContext *ctx)
/* dlmzb */
static void gen_dlmzb(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
+ TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 89/91] target/tricore: Use min/max for saturate
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (87 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 88/91] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 90/91] tcg: Drop tcg_const_*_vec Richard Henderson
` (2 subsequent siblings)
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Use tcg_constant_i32 for the bounds.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a3a5263a5d..2646cb3eb5 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2443,21 +2443,13 @@ gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
{
- TCGv sat_neg = tcg_const_i32(low);
- TCGv temp = tcg_const_i32(up);
-
- /* sat_neg = (arg < low ) ? low : arg; */
- tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
-
- /* ret = (sat_neg > up ) ? up : sat_neg; */
- tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
+ tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low));
+ tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up));
}
static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
{
- TCGv temp = tcg_const_i32(up);
- /* sat_neg = (arg > up ) ? up : arg; */
- tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
+ tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up));
}
static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 90/91] tcg: Drop tcg_const_*_vec
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (88 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 89/91] target/tricore: Use min/max for saturate Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-09 20:05 ` [PULL v2 91/91] tcg: Drop tcg_const_* Richard Henderson
2023-03-11 17:16 ` [PULL v2 00/91] tcg patch queue Peter Maydell
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Replace with tcg_constant_vec*.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 4 ----
tcg/tcg-op-vec.c | 34 ++--------------------------------
tcg/i386/tcg-target.c.inc | 9 ++++-----
3 files changed, 6 insertions(+), 41 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 00c4fbe613..d620012c48 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -999,10 +999,6 @@ void tcg_optimize(TCGContext *s);
/* Allocate a new temporary and initialize it with a constant. */
TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
-TCGv_vec tcg_const_zeros_vec(TCGType);
-TCGv_vec tcg_const_ones_vec(TCGType);
-TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
-TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
/*
* Locate or create a read-only temporary that is a constant.
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 0f023f42c6..aeeb2435cb 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -229,32 +229,6 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
}
}
-TCGv_vec tcg_const_zeros_vec(TCGType type)
-{
- TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(MO_64, ret, 0);
- return ret;
-}
-
-TCGv_vec tcg_const_ones_vec(TCGType type)
-{
- TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(MO_64, ret, -1);
- return ret;
-}
-
-TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec m)
-{
- TCGTemp *t = tcgv_vec_temp(m);
- return tcg_const_zeros_vec(t->base_type);
-}
-
-TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
-{
- TCGTemp *t = tcgv_vec_temp(m);
- return tcg_const_ones_vec(t->base_type);
-}
-
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
{
TCGTemp *rt = tcgv_vec_temp(r);
@@ -431,9 +405,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
- TCGv_vec t = tcg_const_ones_vec_matching(r);
- tcg_gen_xor_vec(0, r, a, t);
- tcg_temp_free_vec(t);
+ tcg_gen_xor_vec(0, r, a, tcg_constant_vec_matching(r, 0, -1));
}
tcg_swap_vecop_list(hold_list);
}
@@ -446,9 +418,7 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
hold_list = tcg_swap_vecop_list(NULL);
if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) {
- TCGv_vec t = tcg_const_zeros_vec_matching(r);
- tcg_gen_sub_vec(vece, r, t, a);
- tcg_temp_free_vec(t);
+ tcg_gen_sub_vec(vece, r, tcg_constant_vec_matching(r, vece, 0), a);
}
tcg_swap_vecop_list(hold_list);
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 4060a35cf6..4444eb9234 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3651,6 +3651,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,
break;
case MO_64:
+ t1 = tcg_temp_new_vec(type);
if (imm <= 32) {
/*
* We can emulate a small sign extend by performing an arithmetic
@@ -3659,24 +3660,22 @@ static void expand_vec_sari(TCGType type, unsigned vece,
* does not, so we have to bound the smaller shift -- we get the
* same result in the high half either way.
*/
- t1 = tcg_temp_new_vec(type);
tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
tcg_gen_shri_vec(MO_64, v0, v1, imm);
vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
tcgv_vec_arg(v0), tcgv_vec_arg(v0),
tcgv_vec_arg(t1), 0xaa);
- tcg_temp_free_vec(t1);
} else {
/* Otherwise we will need to use a compare vs 0 to produce
* the sign-extend, shift and merge.
*/
- t1 = tcg_const_zeros_vec(type);
- tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
+ tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1,
+ tcg_constant_vec(type, MO_64, 0), v1);
tcg_gen_shri_vec(MO_64, v0, v1, imm);
tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
tcg_gen_or_vec(MO_64, v0, v0, t1);
- tcg_temp_free_vec(t1);
}
+ tcg_temp_free_vec(t1);
break;
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL v2 91/91] tcg: Drop tcg_const_*
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (89 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 90/91] tcg: Drop tcg_const_*_vec Richard Henderson
@ 2023-03-09 20:05 ` Richard Henderson
2023-03-11 17:16 ` [PULL v2 00/91] tcg patch queue Peter Maydell
91 siblings, 0 replies; 94+ messages in thread
From: Richard Henderson @ 2023-03-09 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
These functions are no longer used.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 4 ----
include/tcg/tcg.h | 6 ------
tcg/tcg.c | 16 ----------------
3 files changed, 26 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 70856147c5..dff17c7072 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -1089,9 +1089,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
-#define tcg_const_tl tcg_const_i64
#define tcg_constant_tl tcg_constant_i64
-#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_add2_tl tcg_gen_add2_i64
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
@@ -1205,9 +1203,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
-#define tcg_const_tl tcg_const_i32
#define tcg_constant_tl tcg_constant_i32
-#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_add2_tl tcg_gen_add2_i32
#define tcg_gen_sub2_tl tcg_gen_sub2_i32
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index d620012c48..5cfaa53938 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -996,10 +996,6 @@ void tcg_remove_ops_after(TCGOp *op);
void tcg_optimize(TCGContext *s);
-/* Allocate a new temporary and initialize it with a constant. */
-TCGv_i32 tcg_const_i32(int32_t val);
-TCGv_i64 tcg_const_i64(int64_t val);
-
/*
* Locate or create a read-only temporary that is a constant.
* This kind of temporary need not be freed, but for convenience
@@ -1021,10 +1017,8 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
#if UINTPTR_MAX == UINT32_MAX
-# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
#else
-# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
#endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index d2993826c8..bb52bc060b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1445,22 +1445,6 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val)
return tcg_constant_vec(t->base_type, vece, val);
}
-TCGv_i32 tcg_const_i32(int32_t val)
-{
- TCGv_i32 t0;
- t0 = tcg_temp_new_i32();
- tcg_gen_movi_i32(t0, val);
- return t0;
-}
-
-TCGv_i64 tcg_const_i64(int64_t val)
-{
- TCGv_i64 t0;
- t0 = tcg_temp_new_i64();
- tcg_gen_movi_i64(t0, val);
- return t0;
-}
-
/* Return true if OP may appear in the opcode stream.
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PULL v2 00/91] tcg patch queue
2023-03-09 20:04 [PULL v2 00/91] tcg patch queue Richard Henderson
` (90 preceding siblings ...)
2023-03-09 20:05 ` [PULL v2 91/91] tcg: Drop tcg_const_* Richard Henderson
@ 2023-03-11 17:16 ` Peter Maydell
91 siblings, 0 replies; 94+ messages in thread
From: Peter Maydell @ 2023-03-11 17:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 9 Mar 2023 at 20:05, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 66a6aa8f9a56a6317e074b1f5e269fecdf4ad782:
>
> Merge tag 'vfio-updates-20230307.1' of https://gitlab.com/alex.williamson/qemu into staging (2023-03-09 15:19:44 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230309
>
> for you to fetch changes up to 29fc660789547ceb5d6565e7fc39d8c1f65dd157:
>
> tcg: Drop tcg_const_* (2023-03-09 11:55:56 -0800)
>
> ----------------------------------------------------------------
> accel/tcg: Fix NB_MMU_MODES to 16
> Balance of the target/ patchset which eliminates tcg_temp_free
> Balance of the target/ patchset which eliminates tcg_const
>
> ----------------------------------------------------------------
This seems to cause failures in the avocado-system-debian
job on various Arm boot tests. Failed on 3 retries of the
job, so it's not an intermittent:
https://gitlab.com/qemu-project/qemu/-/jobs/3913509263
https://gitlab.com/qemu-project/qemu/-/jobs/3913982271
https://gitlab.com/qemu-project/qemu/-/jobs/3916177988
-- PMM
^ permalink raw reply [flat|nested] 94+ messages in thread