From: Huang Rui <ray.huang@amd.com>
To: "Gerd Hoffmann" <kraxel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Stefano Stabellini" <sstabellini@kernel.org>,
"Anthony PERARD" <anthony.perard@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Antonio Caggiano" <antonio.caggiano@collabora.com>,
"Dr . David Alan Gilbert" <dgilbert@redhat.com>,
"Robert Beckett" <bob.beckett@collabora.com>,
qemu-devel@nongnu.org, xen-devel@lists.xenproject.org
Cc: "Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Stewart Hildebrand" <Stewart.Hildebrand@amd.com>,
"Xenia Ragiadakou" <burzalodowa@gmail.com>,
"Honglei Huang" <honglei1.huang@amd.com>,
"Julia Zhang" <julia.zhang@amd.com>,
"Chen Jiqian" <Jiqian.Chen@amd.com>
Subject: [RFC QEMU PATCH 06/18] virtio-gpu: Resource UUID
Date: Sun, 12 Mar 2023 17:22:32 +0800 [thread overview]
Message-ID: <20230312092244.451465-7-ray.huang@amd.com> (raw)
In-Reply-To: <20230312092244.451465-1-ray.huang@amd.com>
From: Antonio Caggiano <antonio.caggiano@collabora.com>
Enable resource UUID feature and implement command resource assign UUID.
This is done by introducing a hash table to map resource IDs to their
UUIDs.
Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
---
hw/display/trace-events | 1 +
hw/display/virtio-gpu-base.c | 2 ++
hw/display/virtio-gpu-virgl.c | 11 +++++++++
hw/display/virtio-gpu.c | 41 ++++++++++++++++++++++++++++++++++
include/hw/virtio/virtio-gpu.h | 4 ++++
5 files changed, 59 insertions(+)
diff --git a/hw/display/trace-events b/hw/display/trace-events
index 0c0ffcbe42..6632344322 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -41,6 +41,7 @@ virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t size) "res 0x%x, size %" P
virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x"
virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x"
virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x"
+virtio_gpu_cmd_res_assign_uuid(uint32_t res) "res 0x%x"
virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x"
virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x"
virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x"
diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c
index 5cb71e71ad..54792aa501 100644
--- a/hw/display/virtio-gpu-base.c
+++ b/hw/display/virtio-gpu-base.c
@@ -219,6 +219,8 @@ virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features,
features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT);
}
+ features |= (1 << VIRTIO_GPU_F_RESOURCE_UUID);
+
return features;
}
diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c
index 41712b79ee..a3c388f907 100644
--- a/hw/display/virtio-gpu-virgl.c
+++ b/hw/display/virtio-gpu-virgl.c
@@ -45,6 +45,10 @@ static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
args.nr_samples = 0;
args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
virgl_renderer_resource_create(&args, NULL, 0);
+
+ struct virtio_gpu_simple_resource *res = g_new0(struct virtio_gpu_simple_resource, 1);
+ res->resource_id = c2d.resource_id;
+ QTAILQ_INSERT_HEAD(&g->reslist, res, next);
}
static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
@@ -69,6 +73,10 @@ static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
args.nr_samples = c3d.nr_samples;
args.flags = c3d.flags;
virgl_renderer_resource_create(&args, NULL, 0);
+
+ struct virtio_gpu_simple_resource *res = g_new0(struct virtio_gpu_simple_resource, 1);
+ res->resource_id = c3d.resource_id;
+ QTAILQ_INSERT_HEAD(&g->reslist, res, next);
}
static void virgl_cmd_resource_unref(VirtIOGPU *g,
@@ -621,6 +629,9 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
/* TODO add security */
virgl_cmd_ctx_detach_resource(g, cmd);
break;
+ case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID:
+ virtio_gpu_resource_assign_uuid(g, cmd);
+ break;
case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
virgl_cmd_get_capset_info(g, cmd);
break;
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 62239dee0f..c7d1e52cb5 100644
--- a/hw/display/virtio-gpu.c
+++ b/hw/display/virtio-gpu.c
@@ -940,6 +940,37 @@ virtio_gpu_resource_detach_backing(VirtIOGPU *g,
virtio_gpu_cleanup_mapping(g, res);
}
+void virtio_gpu_resource_assign_uuid(VirtIOGPU *g,
+ struct virtio_gpu_ctrl_command *cmd)
+{
+ struct virtio_gpu_simple_resource *res;
+ struct virtio_gpu_resource_assign_uuid assign;
+ struct virtio_gpu_resp_resource_uuid resp;
+ QemuUUID *uuid = NULL;
+
+ VIRTIO_GPU_FILL_CMD(assign);
+ virtio_gpu_bswap_32(&assign, sizeof(assign));
+ trace_virtio_gpu_cmd_res_assign_uuid(assign.resource_id);
+
+ res = virtio_gpu_find_check_resource(g, assign.resource_id, false, __func__, &cmd->error);
+ if (!res) {
+ return;
+ }
+
+ memset(&resp, 0, sizeof(resp));
+ resp.hdr.type = VIRTIO_GPU_RESP_OK_RESOURCE_UUID;
+
+ uuid = g_hash_table_lookup(g->resource_uuids, GUINT_TO_POINTER(assign.resource_id));
+ if (!uuid) {
+ uuid = g_new(QemuUUID, 1);
+ qemu_uuid_generate(uuid);
+ g_hash_table_insert(g->resource_uuids, GUINT_TO_POINTER(assign.resource_id), uuid);
+ }
+
+ memcpy(resp.uuid, uuid, sizeof(QemuUUID));
+ virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
+}
+
void virtio_gpu_simple_process_cmd(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
@@ -988,6 +1019,9 @@ void virtio_gpu_simple_process_cmd(VirtIOGPU *g,
case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
virtio_gpu_resource_detach_backing(g, cmd);
break;
+ case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID:
+ virtio_gpu_resource_assign_uuid(g, cmd);
+ break;
default:
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
break;
@@ -1348,12 +1382,15 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
QTAILQ_INIT(&g->reslist);
QTAILQ_INIT(&g->cmdq);
QTAILQ_INIT(&g->fenceq);
+
+ g->resource_uuids = g_hash_table_new_full(NULL, NULL, NULL, g_free);
}
static void virtio_gpu_device_unrealize(DeviceState *qdev)
{
VirtIOGPU *g = VIRTIO_GPU(qdev);
+ g_hash_table_destroy(g->resource_uuids);
qemu_bh_delete(g->cursor_bh);
qemu_bh_delete(g->ctrl_bh);
@@ -1383,6 +1420,10 @@ void virtio_gpu_reset(VirtIODevice *vdev)
g_free(cmd);
}
+ if (g->resource_uuids) {
+ g_hash_table_remove_all(g->resource_uuids);
+ }
+
virtio_gpu_base_reset(VIRTIO_GPU_BASE(vdev));
}
diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h
index ef02190f97..0a44aea4ee 100644
--- a/include/hw/virtio/virtio-gpu.h
+++ b/include/hw/virtio/virtio-gpu.h
@@ -200,6 +200,8 @@ struct VirtIOGPU {
QTAILQ_HEAD(, VGPUDMABuf) bufs;
VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS];
} dmabuf;
+
+ GHashTable *resource_uuids;
};
struct VirtIOGPUClass {
@@ -273,6 +275,8 @@ int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
uint32_t *niov);
void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
struct iovec *iov, uint32_t count);
+void virtio_gpu_resource_assign_uuid(VirtIOGPU *g,
+ struct virtio_gpu_ctrl_command *cmd);
void virtio_gpu_process_cmdq(VirtIOGPU *g);
void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
void virtio_gpu_reset(VirtIODevice *vdev);
--
2.25.1
next prev parent reply other threads:[~2023-03-12 9:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-12 9:22 [RFC QEMU PATCH 00/18] Add VirtIO GPU and Passthrough GPU support on Xen Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 01/18] virtio: Add shared memory capability Huang Rui
2023-03-13 9:01 ` Philippe Mathieu-Daudé
2023-03-12 9:22 ` [RFC QEMU PATCH 02/18] virtio-gpu: hostmem Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 03/18] virtio-gpu: Handle resource blob commands Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 04/18] virtio-gpu: CONTEXT_INIT feature Huang Rui
2023-03-13 9:06 ` Philippe Mathieu-Daudé
2023-03-12 9:22 ` [RFC QEMU PATCH 05/18] virtio-gpu: Unrealize Huang Rui
2023-03-12 9:22 ` Huang Rui [this message]
2023-03-12 9:22 ` [RFC QEMU PATCH 07/18] virtio-gpu: Support Venus capset Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 08/18] virtio-gpu: Initialize Venus Huang Rui
2023-03-12 17:51 ` Dmitry Osipenko
2023-03-13 2:22 ` Dmitry Osipenko
2023-03-13 15:57 ` Huang Rui
2023-03-13 15:55 ` Huang Rui
2023-03-15 23:14 ` Dmitry Osipenko
2023-03-24 13:22 ` Huang Rui
2023-04-03 21:03 ` Dmitry Osipenko
2023-03-12 9:22 ` [RFC QEMU PATCH 09/18] meson: Enable virglrenderer unstable APIs Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 10/18] virtio-gpu: Handle set scanout blob command Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 11/18] virtio-gpu: make blob scanout use dmabuf fd Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 12/18] softmmu: Fix the size to map cache with xen for host virtual address Huang Rui
2023-03-18 0:31 ` Stefano Stabellini
2023-03-12 9:22 ` [RFC QEMU PATCH 13/18] hw/i386/xen/xen-hvm: Introduce xen_ram_block_check function Huang Rui
2023-03-18 0:38 ` Stefano Stabellini
2023-03-12 9:22 ` [RFC QEMU PATCH 14/18] softmmu: Add ram block check to map the xen ram memory Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 15/18] softmmu: Enable qemu ram allocation with fd for Xen Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 16/18] virtio-gpu: fix hw-display-virtio-gpu.so undefined symbol virtio_gpu_virgl_resource_unmap Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 17/18] virtio-gpu: Add video hardware accelerate support for virgl Huang Rui
2023-03-12 9:22 ` [RFC QEMU PATCH 18/18] xen: translate irq of host pci device to gsi Huang Rui
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