From: Ilya Leoshkevich <iii@linux.ibm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
David Hildenbrand <david@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>,
qemu-s390x@nongnu.org, qemu-devel@nongnu.org,
Ilya Leoshkevich <iii@linux.ibm.com>,
Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Subject: [PATCH v2 05/12] target/s390x: Handle LLGFRL from non-aligned addresses
Date: Mon, 13 Mar 2023 16:38:37 +0100 [thread overview]
Message-ID: <20230313153844.9231-6-iii@linux.ibm.com> (raw)
In-Reply-To: <20230313153844.9231-1-iii@linux.ibm.com>
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/s390x/tcg/insn-data.h.inc | 6 +++---
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 5aff4c0873a..3abd2dbedd5 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -502,16 +502,16 @@
C(0xc405, LHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16s, 0)
C(0xc404, LGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16s, 0)
/* LOAD HIGH */
- C(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0)
+ D(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0, 0)
/* LOAG HIGH AND TRAP */
C(0xe3c8, LFHAT, RXY_a, LAT, 0, m2_32u, r1, 0, lfhat, 0)
/* LOAD LOGICAL */
C(0xb916, LLGFR, RRE, Z, 0, r2_32u, 0, r1, mov2, 0)
- C(0xe316, LLGF, RXY_a, Z, 0, a2, r1, 0, ld32u, 0)
+ D(0xe316, LLGF, RXY_a, Z, 0, a2, r1, 0, ld32u, 0, 0)
/* LOAD LOGICAL AND TRAP */
C(0xe39d, LLGFAT, RXY_a, LAT, 0, a2, r1, 0, llgfat, 0)
/* LOAD LOGICAL RELATIVE LONG */
- C(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0)
+ D(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0, MO_ALIGN)
/* LOAD LOGICAL CHARACTER */
C(0xb994, LLCR, RRE, EI, 0, r2_8u, 0, r1_32, mov2, 0)
C(0xb984, LLGCR, RRE, EI, 0, r2_8u, 0, r1, mov2, 0)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 5033767cef4..6ceb14de92f 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2846,7 +2846,8 @@ static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)
static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
+ MO_TEUL | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
next prev parent reply other threads:[~2023-03-13 15:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-13 15:38 [PATCH v2 00/12] target/s390x: Handle unaligned accesses Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 01/12] target/s390x: Handle branching to odd addresses Ilya Leoshkevich
2023-03-13 19:54 ` Richard Henderson
2023-03-13 15:38 ` [PATCH v2 02/12] target/s390x: Handle EXECUTE of " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 03/12] target/s390x: Handle LGRL from non-aligned addresses Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 04/12] target/s390x: Handle LRL and LGFRL " Ilya Leoshkevich
2023-03-13 15:38 ` Ilya Leoshkevich [this message]
2023-03-13 15:38 ` [PATCH v2 06/12] target/s390x: Handle CRL and CGFRL with " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 07/12] target/s390x: Handle CGRL and CLGRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 08/12] target/s390x: Handle CLRL and CLGFRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 09/12] target/s390x: Handle STRL to " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 10/12] target/s390x: Handle STGRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 11/12] target/s390x: Update do_unaligned_access() comment Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 12/12] tests/tcg/s390x: Test unaligned accesses Ilya Leoshkevich
2023-03-15 18:09 ` Thomas Huth
2023-03-15 18:13 ` Ilya Leoshkevich
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