From: Thomas Huth <thuth@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Ilya Leoshkevich <iii@linux.ibm.com>,
Nina Schoetterl-Glausch <nsg@linux.ibm.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 11/24] target/s390x: Handle LGRL from non-aligned addresses
Date: Mon, 20 Mar 2023 14:03:17 +0100 [thread overview]
Message-ID: <20230320130330.406378-12-thuth@redhat.com> (raw)
In-Reply-To: <20230320130330.406378-1-thuth@redhat.com>
From: Ilya Leoshkevich <iii@linux.ibm.com>
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230316164428.275147-4-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
target/s390x/tcg/insn-data.h.inc | 6 +++---
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 6fe8ca5143..d439d80350 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -414,7 +414,7 @@
C(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0)
C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0)
C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0)
- C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0)
+ D(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0, 0)
C(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0)
F(0x2800, LDR, RR_a, Z, 0, f2, 0, f1, mov2, 0, IF_AFP1 | IF_AFP2)
F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
@@ -427,7 +427,7 @@
C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0)
/* LOAD RELATIVE LONG */
C(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0)
- C(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0)
+ D(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0, MO_ALIGN)
C(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0)
/* LOAD ADDRESS */
C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0)
@@ -457,7 +457,7 @@
C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64)
C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64)
C(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64)
- C(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64)
+ D(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64, 0)
C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64)
F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP)
F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index a6d81ed16b..e76f05f83b 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2782,7 +2782,8 @@ static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
static DisasJumpType op_ld64(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),
+ MO_TEUQ | s->insn->data);
return DISAS_NEXT;
}
--
2.31.1
next prev parent reply other threads:[~2023-03-20 13:07 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 13:03 [PULL 00/24] s390x and misc patches for 8.0-rc1 Thomas Huth
2023-03-20 13:03 ` [PULL 01/24] MAINTAINERS: Mark the Nios II CPU as orphan Thomas Huth
2023-03-20 13:03 ` [PULL 02/24] target/s390x: Fix LPSW Thomas Huth
2023-03-20 13:03 ` [PULL 03/24] target/s390x: Implement Early Exception Recognition Thomas Huth
2023-03-20 13:03 ` [PULL 04/24] tests/tcg/s390x: Add PSW modification tests Thomas Huth
2023-03-20 13:03 ` [PULL 05/24] target/s390x: Fix R[NOX]SBG with T=1 Thomas Huth
2023-03-20 13:03 ` [PULL 06/24] tests/tcg/s390x: Add rxsbg.c Thomas Huth
2023-03-20 13:03 ` [PULL 07/24] target/s390x: Fix EXECUTE of relative long instructions Thomas Huth
2023-03-20 13:03 ` [PULL 08/24] tests/tcg/s390x: Add ex-relative-long.c Thomas Huth
2023-03-20 13:03 ` [PULL 09/24] target/s390x: Handle branching to odd addresses Thomas Huth
2023-03-20 13:03 ` [PULL 10/24] target/s390x: Handle EXECUTE of " Thomas Huth
2023-03-20 13:03 ` Thomas Huth [this message]
2023-03-20 13:03 ` [PULL 12/24] target/s390x: Handle LRL and LGFRL from non-aligned addresses Thomas Huth
2023-03-20 13:03 ` [PULL 13/24] target/s390x: Handle LLGFRL " Thomas Huth
2023-03-20 13:03 ` [PULL 14/24] target/s390x: Handle CRL and CGFRL with " Thomas Huth
2023-03-20 13:03 ` [PULL 15/24] target/s390x: Handle CGRL and CLGRL " Thomas Huth
2023-03-20 13:03 ` [PULL 16/24] target/s390x: Handle CLRL and CLGFRL " Thomas Huth
2023-03-20 13:03 ` [PULL 17/24] target/s390x: Handle STRL to " Thomas Huth
2023-03-20 13:03 ` [PULL 18/24] target/s390x: Handle STGRL " Thomas Huth
2023-03-20 13:03 ` [PULL 19/24] target/s390x: Update do_unaligned_access() comment Thomas Huth
2023-03-20 13:03 ` [PULL 20/24] tests/tcg/s390x: Test unaligned accesses Thomas Huth
2023-03-20 13:03 ` [PULL 21/24] target/s390x/tcg/mem_helper: Remove bad assert() statement Thomas Huth
2023-03-20 13:03 ` [PULL 22/24] tests/unit/test-blockjob: Disable complete_in_standby test Thomas Huth
2023-03-20 13:03 ` [PULL 23/24] qemu/osdep: Switch position of "extern" and "G_NORETURN" Thomas Huth
2023-03-20 13:03 ` [PULL 24/24] replace TABs with spaces Thomas Huth
2023-03-20 14:02 ` [PULL 00/24] s390x and misc patches for 8.0-rc1 Thomas Huth
2023-03-20 15:10 ` Peter Maydell
2023-03-20 15:27 ` Philippe Mathieu-Daudé
2023-03-20 15:36 ` Thomas Huth
2023-03-20 17:50 ` Peter Maydell
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