From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Michael Tsirkin <mst@redhat.com>, <qemu-devel@nongnu.org>
Cc: <linuxarm@huawei.com>, Fan Ni <fan.ni@samsung.com>,
Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>
Subject: [RESEND PATCH 1/2] hw/cxl: Fix endian handling for decoder commit.
Date: Wed, 22 Mar 2023 10:27:30 +0000 [thread overview]
Message-ID: <20230322102731.4219-2-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230322102731.4219-1-Jonathan.Cameron@huawei.com>
Not a real problem yet as all supported architectures are
little endian, but continue to tidy these up when touching
code for other reasons.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-component-utils.c | 10 ++++------
hw/mem/cxl_type3.c | 9 ++++++---
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index b665d4f565..a3e6cf75cf 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -47,14 +47,12 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
break;
}
- memory_region_transaction_begin();
- stl_le_p((uint8_t *)cache_mem + offset, value);
if (should_commit) {
- ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
- ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
- ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
+ value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
+ value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
+ value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
}
- memory_region_transaction_commit();
+ stl_le_p((uint8_t *)cache_mem + offset, value);
}
static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index abe60b362c..846089ccda 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -314,14 +314,17 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
{
ComponentRegisters *cregs = &ct3d->cxl_cstate.crb;
uint32_t *cache_mem = cregs->cache_mem_registers;
+ uint32_t ctrl;
assert(which == 0);
+ ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL);
/* TODO: Sanity checks that the decoder is possible */
- ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
- ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
+ ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
+ ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0);
+ ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
- ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
+ stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL, ctrl);
}
static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
--
2.37.2
next prev parent reply other threads:[~2023-03-22 10:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 10:27 [RESEND PATCH 0/2] hw/cxl: Fix decoder commit and uncommit handling Jonathan Cameron via
2023-03-22 10:27 ` Jonathan Cameron via [this message]
2023-03-22 10:34 ` [RESEND PATCH 1/2] hw/cxl: Fix endian handling for decoder commit Philippe Mathieu-Daudé
2023-03-22 10:27 ` [RESEND PATCH 2/2] hw/cxl: Fix incorrect reset of commit and associated clearing of committed Jonathan Cameron via
2023-03-22 10:33 ` Jonathan Cameron via
2023-03-22 16:21 ` Fan Ni
2023-03-24 14:01 ` Jonathan Cameron via
2023-03-24 17:05 ` Dave Jiang
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