From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Vincent Dehors" <vincent.dehors@smile.fr>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
Subject: [PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection
Date: Wed, 22 Mar 2023 16:25:35 -0400 [thread overview]
Message-ID: <20230322202541.1404058-3-aaron@os.amperecomputing.com> (raw)
In-Reply-To: <20230322202541.1404058-1-aaron@os.amperecomputing.com>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
---
target/arm/cpu.h | 65 +++++++++++++++++++++++++++++++++--
target/arm/tcg/pauth_helper.c | 2 +-
2 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f0f27f259d..868d844d5a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3705,18 +3705,77 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
(FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
- FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
+ FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0 ||
+ (id->id_aa64isar2 &
+ (FIELD_DP64(0, ID_AA64ISAR2, APA3, 0xf) |
+ FIELD_DP64(0, ID_AA64ISAR2, GPA3, 0xf))) != 0;
}
-static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
+static inline bool isar_feature_aa64_pauth_arch_qarma5(const ARMISARegisters *id)
{
/*
- * Return true if pauth is enabled with the architected QARMA algorithm.
+ * Return true if pauth is enabled with the architected QARMA5 algorithm.
* QEMU will always set APA+GPA to the same value.
*/
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
}
+static inline bool isar_feature_aa64_pauth_arch_qarma3(const ARMISARegisters *id)
+{
+ /*
+ * Return true if pauth is enabled with the architected QARMA3 algorithm.
+ * QEMU will always set APA3+GPA3 to the same result.
+ */
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
+}
+
+static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_pauth_arch_qarma5(id) ||
+ isar_feature_aa64_pauth_arch_qarma3(id);
+}
+
+static inline int isar_feature_pauth_get_features(const ARMISARegisters *id)
+{
+ if (isar_feature_aa64_pauth_arch_qarma5(id)) {
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA);
+ } else if (isar_feature_aa64_pauth_arch_qarma3(id)) {
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3);
+ } else {
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API);
+ }
+}
+
+static inline bool isar_feature_aa64_pauth_epac(const ARMISARegisters *id)
+{
+ /*
+ * Note that unlike most AArch64 features, EPAC is treated (in the ARM
+ * psedocode, at least) as not being implemented by larger values of this
+ * field. Our usage of '>=' rather than '==' here causes our implementation
+ * of PAC logic to diverge from ARM pseudocode - we must check that
+ * isar_feature_aa64_pauth2() returns false AND
+ * isar_feature_aa64_pauth_epac() returns true, where the pseudocode reads
+ * as if EPAC is not implemented if the value of this register is > 0b10.
+ * See the implementation of pauth_addpac() for an example.
+ */
+ return isar_feature_pauth_get_features(id) >= 0b0010;
+}
+
+static inline bool isar_feature_aa64_pauth2(const ARMISARegisters *id)
+{
+ return isar_feature_pauth_get_features(id) >= 0b0011;
+}
+
+static inline bool isar_feature_aa64_fpac(const ARMISARegisters *id)
+{
+ return isar_feature_pauth_get_features(id) >= 0b0100;
+}
+
+static inline bool isar_feature_aa64_fpac_combine(const ARMISARegisters *id)
+{
+ return isar_feature_pauth_get_features(id) >= 0b0101;
+}
+
static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index 20f347332d..6bb3b5b9e5 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -282,7 +282,7 @@ static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier,
static uint64_t pauth_computepac(CPUARMState *env, uint64_t data,
uint64_t modifier, ARMPACKey key)
{
- if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) {
+ if (cpu_isar_feature(aa64_pauth_arch_qarma5, env_archcpu(env))) {
return pauth_computepac_architected(data, modifier, key);
} else {
return pauth_computepac_impdef(data, modifier, key);
--
2.25.1
next prev parent reply other threads:[~2023-03-22 20:27 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 20:25 [PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features Aaron Lindsay
2023-03-22 20:25 ` [PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1 Aaron Lindsay
2023-03-23 17:33 ` Richard Henderson
2023-03-22 20:25 ` Aaron Lindsay [this message]
2023-03-23 17:42 ` [PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection Richard Henderson
2023-03-22 20:25 ` [PATCH v3 3/8] target/arm: Implement v8.3 QARMA3 PAC cipher Aaron Lindsay
2023-03-22 20:25 ` [PATCH v3 4/8] target/arm: Implement v8.3 EnhancedPAC Aaron Lindsay
2023-03-22 20:25 ` [PATCH v3 5/8] target/arm: Implement v8.3 Pauth2 Aaron Lindsay
2023-03-22 20:25 ` [PATCH v3 6/8] targer/arm: Inform helpers whether a PAC instruction is 'combined' Aaron Lindsay
2023-03-22 20:25 ` [PATCH v3 7/8] target/arm: Implement v8.3 FPAC and FPACCOMBINE Aaron Lindsay
2023-03-23 17:48 ` Richard Henderson
2023-03-22 20:25 ` [PATCH v3 8/8] target/arm: Add CPU property for QARMA3, enable FPACCombined by default Aaron Lindsay
2023-03-23 17:51 ` Richard Henderson
-- strict thread matches above, loose matches on Subject: below --
2023-06-09 17:23 [PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features Aaron Lindsay
2023-06-09 17:23 ` [PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection Aaron Lindsay
2023-06-09 20:51 ` Richard Henderson
2023-06-12 13:19 ` Aaron Lindsay
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