From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 1/8] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
Date: Fri, 24 Mar 2023 20:38:02 +0800 [thread overview]
Message-ID: <20230324123809.107714-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230324123809.107714-1-liweiwei@iscas.ac.cn>
The assignment is done under the condition riscv_cpu_virt_enabled()=true.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu_helper.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 824f0cbd92..e140d6a8d0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1706,9 +1706,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_swap_hypervisor_regs(env);
env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
env->priv);
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
- riscv_cpu_virt_enabled(env));
-
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
htval = env->guest_phys_fault_addr;
--
2.25.1
next prev parent reply other threads:[~2023-03-24 15:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-24 12:38 [PATCH 0/8] target/riscv: Simplification for RVH related check and code style fix Weiwei Li
2023-03-24 12:38 ` Weiwei Li [this message]
2023-03-24 18:04 ` [PATCH 1/8] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Richard Henderson
2023-03-24 12:38 ` [PATCH 2/8] target/riscv: Remove redundant check on RVH Weiwei Li
2023-03-24 18:04 ` Richard Henderson
2023-03-24 12:38 ` [PATCH 3/8] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Weiwei Li
2023-03-24 18:05 ` Richard Henderson
2023-03-24 12:38 ` [PATCH 4/8] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Weiwei Li
2023-03-24 18:10 ` Richard Henderson
2023-03-24 12:38 ` [PATCH 5/8] target/riscv: Remove redundant parentheses Weiwei Li
2023-03-24 18:10 ` Richard Henderson
2023-03-24 12:38 ` [PATCH 6/8] target/riscv: Fix format for indentation Weiwei Li
2023-03-25 14:23 ` LIU Zhiwei
2023-03-26 12:38 ` liweiwei
2023-03-24 12:38 ` [PATCH 7/8] target/riscv: Fix format for comments Weiwei Li
2023-03-24 18:12 ` Richard Henderson
2023-03-24 12:38 ` [PATCH 8/8] target/riscv: Fix lines with over 80 characters Weiwei Li
2023-03-25 15:05 ` [PATCH 0/8] target/riscv: Simplification for RVH related check and code style fix LIU Zhiwei
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