From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Date: Thu, 30 Mar 2023 11:46:36 +0800 [thread overview]
Message-ID: <20230330034636.44585-1-liweiwei@iscas.ac.cn> (raw)
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c36..4b730cd492 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
static bool check_access(DisasContext *ctx)
{
if (!ctx->hlsx) {
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ offsetof(CPURISCVState, bins));
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
--
2.25.1
next reply other threads:[~2023-03-30 3:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 3:46 Weiwei Li [this message]
2023-03-30 11:13 ` [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Daniel Henrique Barboza
2023-04-05 3:55 ` Alistair Francis
2023-04-05 6:43 ` Alistair Francis
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