[PULL 0/6] Misc fixes for 2023-03-30

[PULL 0/6] Misc fixes for 2023-03-30

[Philippe Mathieu-Daudé]

The following changes since commit f00506aeca2f6d92318967693f8da8c713c163f3:

  Merge tag 'pull-tcg-20230328' of https://gitlab.com/rth7680/qemu into staging (2023-03-29 11:19:19 +0100)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/misc-fixes-20230330

for you to fetch changes up to aad3eb1ffeb65205153fb31d81d4f268186cde7a:

  block/dmg: Ignore C99 prototype declaration mismatch from <lzfse.h> (2023-03-30 15:03:36 +0200)

----------------------------------------------------------------
- linux-user:
  . Don't use 16-bit UIDs with SPARC V9
  . Pick MIPS3 CPU by default to run NaN2008 ELF binaries

- HW:
  . Fix invalid GT64120 north bridge endianness register swap
  . Prevent NULL pointer dereference by SMBus devices

- Buildsys:
  . Fix compiling with liblzfse on Darwin

----------------------------------------------------------------

Jiaxun Yang (1):
  hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

Philippe Mathieu-Daudé (4):
  linux-user/sparc: Don't use 16-bit UIDs on SPARC V9
  linux-user/mips: Use P5600 as default CPU to run NaN2008 ELF binaries
  tests/avocado: Enable TuxRun/mips64 (big-endian) test
  block/dmg: Ignore C99 prototype declaration mismatch from <lzfse.h>

Titus Rwantare (1):
  hw/i2c: pmbus: block uninitialised string reads

 linux-user/mips/target_elf.h      |  3 +++
 linux-user/syscall_defs.h         |  2 +-
 block/dmg-lzfse.c                 |  5 +++++
 hw/i2c/pmbus_device.c             |  7 +++++++
 hw/pci-host/gt64120.c             | 18 ++++++------------
 tests/avocado/tuxrun_baselines.py |  1 -
 6 files changed, 22 insertions(+), 14 deletions(-)

-- 
2.38.1

[PULL 1/6] linux-user/sparc: Don't use 16-bit UIDs on SPARC V9

[Philippe Mathieu-Daudé]

The 64-bit SPARC V9 syscall ABI uses 32-bit UIDs. Only enable
the 16-bit UID wrappers for 32-bit SPARC (V7 and V8).

Possibly missed in commit 992f48a036 ("Support for 32 bit
ABI on 64 bit targets (only enabled Sparc64)").

Reported-by: Gregor Riepl <onitake@gmail.com>
Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Tested-by: Zach van Rijn <me@zv.io>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1394
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20230327131910.78564-1-philmd@linaro.org>
---
 linux-user/syscall_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 614a1cbc8e..cc37054cb5 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -61,7 +61,7 @@
 
 #if (defined(TARGET_I386) && defined(TARGET_ABI32)) \
     || (defined(TARGET_ARM) && defined(TARGET_ABI32)) \
-    || defined(TARGET_SPARC) \
+    || (defined(TARGET_SPARC) && defined(TARGET_ABI32)) \
     || defined(TARGET_M68K) || defined(TARGET_SH4) || defined(TARGET_CRIS)
     /* 16 bit uid wrappers emulation */
 #define USE_UID16
-- 
2.38.1

[PULL 2/6] linux-user/mips: Use P5600 as default CPU to run NaN2008 ELF binaries

[Philippe Mathieu-Daudé]

Per the release 6.06 revision history:

 5.03 August 21, 2013

 • ABS2008 and NAN2008 fields of Table 5.7 “FCSR RegisterField
   Descriptions” were optional in release 3 and could be R/W,
   but as of release 5 are required, read-only, and preset by
   hardware.

The P5600 core implements the release 5, and has the ABS2008
and NAN2008 bits set in CP1_fcr31. Therefore it is able to run
ELF binaries compiled with EF_MIPS_NAN2008, such the CIP United
Debian NaN2008 distribution:
http://repo.oss.cipunited.com/mipsel-nan2008/README.txt

In order to run such compiled binaries, select by default the
P5600 core when the ELF 'MIPS_NAN2008' flag is set.

Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20230327162444.388-1-philmd@linaro.org>
---
 linux-user/mips/target_elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/linux-user/mips/target_elf.h b/linux-user/mips/target_elf.h
index a98c9bd6ad..b965e86b2b 100644
--- a/linux-user/mips/target_elf.h
+++ b/linux-user/mips/target_elf.h
@@ -15,6 +15,9 @@ static inline const char *cpu_get_model(uint32_t eflags)
     if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {
         return "R5900";
     }
+    if (eflags & EF_MIPS_NAN2008) {
+        return "P5600";
+    }
     return "24Kf";
 }
 #endif
-- 
2.38.1

[PULL 3/6] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

[Philippe Mathieu-Daudé]

From: Jiaxun Yang <jiaxun.yang@flygoat.com>

145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegionOps") converted CFGADDR/CFGDATA registers to use
PCI_HOST_BRIDGE's accessor facility and enabled byte swap for both
CFGADDR/CFGDATA register.

However CFGADDR as a ISD internal register is not controlled by
MByteSwap bit, it follows endian of all other ISD register, which
means it ties to little endian.

Move mapping of CFGADDR out of gt64120_update_pci_cfgdata_mapping
to disable endian-swapping.

Fixes: 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOps")
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Message-Id: <20230223161958.48696-1-jiaxun.yang@flygoat.com>
[PMD: !!! Note this only fixes little-endian hosts !!! ]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/pci-host/gt64120.c | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
index f226d03420..82c15edb46 100644
--- a/hw/pci-host/gt64120.c
+++ b/hw/pci-host/gt64120.c
@@ -321,9 +321,6 @@ static void gt64120_isd_mapping(GT64120State *s)
 static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
 {
     /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
-    static const MemoryRegionOps *pci_host_conf_ops[] = {
-        &pci_host_conf_be_ops, &pci_host_conf_le_ops
-    };
     static const MemoryRegionOps *pci_host_data_ops[] = {
         &pci_host_data_be_ops, &pci_host_data_le_ops
     };
@@ -339,15 +336,6 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
      * - Table 16: 32-bit PCI Transaction Endianess
      * - Table 158: PCI_0 Command, Offset: 0xc00
      */
-    if (memory_region_is_mapped(&phb->conf_mem)) {
-        memory_region_del_subregion(&s->ISD_mem, &phb->conf_mem);
-        object_unparent(OBJECT(&phb->conf_mem));
-    }
-    memory_region_init_io(&phb->conf_mem, OBJECT(phb),
-                          pci_host_conf_ops[s->regs[GT_PCI0_CMD] & 1],
-                          s, "pci-conf-idx", 4);
-    memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
-                                        &phb->conf_mem, 1);
 
     if (memory_region_is_mapped(&phb->data_mem)) {
         memory_region_del_subregion(&s->ISD_mem, &phb->data_mem);
@@ -1208,6 +1196,12 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
                                 PCI_DEVFN(18, 0), TYPE_PCI_BUS);
 
     pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
+    memory_region_init_io(&phb->conf_mem, OBJECT(phb),
+                          &pci_host_conf_le_ops,
+                          s, "pci-conf-idx", 4);
+    memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
+                                        &phb->conf_mem, 1);
+
 
     /*
      * The whole address space decoded by the GT-64120A doesn't generate
-- 
2.38.1

[PULL 4/6] tests/avocado: Enable TuxRun/mips64 (big-endian) test

[Philippe Mathieu-Daudé]

Now that the previous commit ("hw/mips/gt64xxx_pci: Don't
endian-swap GT_PCI0_CFGADDR") fixed the issue accessing
the GT64120 PCI config-address register on big-endian
targets, we can enable this TuxRun test.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230223220404.63630-1-philmd@linaro.org>
---
 tests/avocado/tuxrun_baselines.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
index c3fb67f5dc..d343376faa 100644
--- a/tests/avocado/tuxrun_baselines.py
+++ b/tests/avocado/tuxrun_baselines.py
@@ -270,7 +270,6 @@ def test_mips32el(self):
         """
         self.common_tuxrun(drive="driver=ide-hd,bus=ide.0,unit=0")
 
-    @skip("QEMU currently broken") # regression against stable QEMU
     def test_mips64(self):
         """
         :avocado: tags=arch:mips64
-- 
2.38.1

[PULL 5/6] hw/i2c: pmbus: block uninitialised string reads

[Philippe Mathieu-Daudé]

From: Titus Rwantare <titusr@google.com>

Devices models calling pmbus_send_string can't be relied upon to
send a non-zero pointer. This logs an error and doesn't segfault.

Reviewed-by: Patrick Venture <venture@google.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230322175513.1550412-5-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/i2c/pmbus_device.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c
index c3d6046784..44fe4eddbb 100644
--- a/hw/i2c/pmbus_device.c
+++ b/hw/i2c/pmbus_device.c
@@ -94,6 +94,13 @@ void pmbus_send64(PMBusDevice *pmdev, uint64_t data)
 
 void pmbus_send_string(PMBusDevice *pmdev, const char *data)
 {
+    if (!data) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: uninitialised read from 0x%02x\n",
+                      __func__, DEVICE(pmdev)->canonical_path, pmdev->code);
+        return;
+    }
+
     size_t len = strlen(data);
     g_assert(len > 0);
     g_assert(len + pmdev->out_buf_len < SMBUS_DATA_MAX_LEN);
-- 
2.38.1

[PULL 6/6] block/dmg: Ignore C99 prototype declaration mismatch from <lzfse.h>

[Philippe Mathieu-Daudé]

When liblzfe (Apple LZFSE compression library) is present
(for example installed via 'brew') on Darwin, QEMU build
fails as:

  Has header "lzfse.h" : YES
  Library lzfse found: YES

    Dependencies
      lzo support                  : NO
      snappy support               : NO
      bzip2 support                : YES
      lzfse support                : YES
      zstd support                 : YES 1.5.2

    User defined options
      dmg                          : enabled
      lzfse                        : enabled

  [221/903] Compiling C object libblock.fa.p/block_dmg-lzfse.c.o
  FAILED: libblock.fa.p/block_dmg-lzfse.c.o
  /opt/homebrew/Cellar/lzfse/1.0/include/lzfse.h:56:43: error: this function declaration is not a prototype [-Werror,-Wstrict-prototypes]
  LZFSE_API size_t lzfse_encode_scratch_size();
                                            ^
                                             void
  /opt/homebrew/Cellar/lzfse/1.0/include/lzfse.h:94:43: error: this function declaration is not a prototype [-Werror,-Wstrict-prototypes]
  LZFSE_API size_t lzfse_decode_scratch_size();
                                            ^
                                             void
  2 errors generated.
  ninja: build stopped: subcommand failed.

This issue has been reported in the lzfse project in 2016:
https://github.com/lzfse/lzfse/issues/3#issuecomment-226574719

Since the project seems unmaintained, simply ignore the
strict-prototypes warning check for the <lzfse.h> header,
similarly to how we deal with the GtkItemFactoryCallback
prototype from <gtk/gtkitemfactory.h>, indirectly included
by <gtk/gtk.h>.

Cc: Julio Faracco <jcfaracco@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20230327151349.97572-1-philmd@linaro.org>
---
 block/dmg-lzfse.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/block/dmg-lzfse.c b/block/dmg-lzfse.c
index 6798cf4fbf..4ea0b9b20d 100644
--- a/block/dmg-lzfse.c
+++ b/block/dmg-lzfse.c
@@ -23,7 +23,12 @@
  */
 #include "qemu/osdep.h"
 #include "dmg.h"
+
+/* Work around a -Wstrict-prototypes warning in LZFSE headers */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
 #include <lzfse.h>
+#pragma GCC diagnostic pop
 
 static int dmg_uncompress_lzfse_do(char *next_in, unsigned int avail_in,
                                    char *next_out, unsigned int avail_out)
-- 
2.38.1

Re: [PULL 0/6] Misc fixes for 2023-03-30

[Peter Maydell]

On Thu, 30 Mar 2023 at 14:19, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> The following changes since commit f00506aeca2f6d92318967693f8da8c713c163f3:
>
>   Merge tag 'pull-tcg-20230328' of https://gitlab.com/rth7680/qemu into staging (2023-03-29 11:19:19 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/philmd/qemu.git tags/misc-fixes-20230330
>
> for you to fetch changes up to aad3eb1ffeb65205153fb31d81d4f268186cde7a:
>
>   block/dmg: Ignore C99 prototype declaration mismatch from <lzfse.h> (2023-03-30 15:03:36 +0200)
>
> ----------------------------------------------------------------
> - linux-user:
>   . Don't use 16-bit UIDs with SPARC V9
>   . Pick MIPS3 CPU by default to run NaN2008 ELF binaries
>
> - HW:
>   . Fix invalid GT64120 north bridge endianness register swap
>   . Prevent NULL pointer dereference by SMBus devices
>
> - Buildsys:
>   . Fix compiling with liblzfse on Darwin
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM

Re: [PULL 1/6] linux-user/sparc: Don't use 16-bit UIDs on SPARC V9

[Laurent Vivier]

On 3/30/23 15:18, Philippe Mathieu-Daudé wrote:
> The 64-bit SPARC V9 syscall ABI uses 32-bit UIDs. Only enable
> the 16-bit UID wrappers for 32-bit SPARC (V7 and V8).
> 
> Possibly missed in commit 992f48a036 ("Support for 32 bit
> ABI on 64 bit targets (only enabled Sparc64)").
> 
> Reported-by: Gregor Riepl <onitake@gmail.com>
> Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
> Tested-by: Zach van Rijn <me@zv.io>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1394
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Acked-by: Laurent Vivier <laurent@vivier.eu>
> Message-Id: <20230327131910.78564-1-philmd@linaro.org>
> ---
>   linux-user/syscall_defs.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
> index 614a1cbc8e..cc37054cb5 100644
> --- a/linux-user/syscall_defs.h
> +++ b/linux-user/syscall_defs.h
> @@ -61,7 +61,7 @@
>   
>   #if (defined(TARGET_I386) && defined(TARGET_ABI32)) \
>       || (defined(TARGET_ARM) && defined(TARGET_ABI32)) \
> -    || defined(TARGET_SPARC) \
> +    || (defined(TARGET_SPARC) && defined(TARGET_ABI32)) \
>       || defined(TARGET_M68K) || defined(TARGET_SH4) || defined(TARGET_CRIS)
>       /* 16 bit uid wrappers emulation */
>   #define USE_UID16

This patch breaks something with LTP (20230127) test fchown05_16 on sid/sparc64:

tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
fchown05.c:44: TPASS: fchown(3, 700, 701), change owner/group ids passed
fchown05.c:44: TPASS: fchown(3, 702, -1), change owner id only passed
fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 702 701
fchown05.c:44: TPASS: fchown(3, 703, 701), change owner id only passed
fchown05.c:44: TPASS: fchown(3, -1, 704), change group id only passed
fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 703 704
fchown05.c:44: TPASS: fchown(3, 703, 705), change group id only passed
fchown05.c:44: TPASS: fchown(3, -1, -1), no change passed
fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 703 705

expected result;

tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
fchown05.c:44: TPASS: fchown(3, 700, 701), change owner/group ids passed
fchown05.c:44: TPASS: fchown(3, 702, -1), change owner id only passed
fchown05.c:44: TPASS: fchown(3, 703, 701), change owner id only passed
fchown05.c:44: TPASS: fchown(3, -1, 704), change group id only passed
fchown05.c:44: TPASS: fchown(3, 703, 705), change group id only passed
fchown05.c:44: TPASS: fchown(3, -1, -1), no change passed

Thanks,
Laurent

Re: [PULL 1/6] linux-user/sparc: Don't use 16-bit UIDs on SPARC V9

[John Paul Adrian Glaubitz]

Hello Laurent!

On Fri, 2023-05-12 at 13:13 +0200, Laurent Vivier wrote:
> This patch breaks something with LTP (20230127) test fchown05_16 on sid/sparc64:
> 
> tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
> fchown05.c:44: TPASS: fchown(3, 700, 701), change owner/group ids passed
> fchown05.c:44: TPASS: fchown(3, 702, -1), change owner id only passed
> fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 702 701
> fchown05.c:44: TPASS: fchown(3, 703, 701), change owner id only passed
> fchown05.c:44: TPASS: fchown(3, -1, 704), change group id only passed
> fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 703 704
> fchown05.c:44: TPASS: fchown(3, 703, 705), change group id only passed
> fchown05.c:44: TPASS: fchown(3, -1, -1), no change passed
> fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 703 705
> 
> expected result;
> 
> tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
> fchown05.c:44: TPASS: fchown(3, 700, 701), change owner/group ids passed
> fchown05.c:44: TPASS: fchown(3, 702, -1), change owner id only passed
> fchown05.c:44: TPASS: fchown(3, 703, 701), change owner id only passed
> fchown05.c:44: TPASS: fchown(3, -1, 704), change group id only passed
> fchown05.c:44: TPASS: fchown(3, 703, 705), change group id only passed
> fchown05.c:44: TPASS: fchown(3, -1, -1), no change passed

Where do these tests reside? I'm not sure I know what LTP is. In any case,
the patch should be correct as QEMU needs to differentiate between 32-bit
and 64-bit SPARC.

Adrian

-- 
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer
`. `'   Physicist
  `-    GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913

Re: [PULL 1/6] linux-user/sparc: Don't use 16-bit UIDs on SPARC V9

[Laurent Vivier]

Le 12/05/2023 à 14:08, John Paul Adrian Glaubitz a écrit :
> Hello Laurent!
> 
> On Fri, 2023-05-12 at 13:13 +0200, Laurent Vivier wrote:
>> This patch breaks something with LTP (20230127) test fchown05_16 on sid/sparc64:
>>
>> tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
>> fchown05.c:44: TPASS: fchown(3, 700, 701), change owner/group ids passed
>> fchown05.c:44: TPASS: fchown(3, 702, -1), change owner id only passed
>> fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 702 701
>> fchown05.c:44: TPASS: fchown(3, 703, 701), change owner id only passed
>> fchown05.c:44: TPASS: fchown(3, -1, 704), change group id only passed
>> fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 703 704
>> fchown05.c:44: TPASS: fchown(3, 703, 705), change group id only passed
>> fchown05.c:44: TPASS: fchown(3, -1, -1), no change passed
>> fchown05.c:49: TFAIL: testfile: incorrect ownership set, expected 703 705
>>
>> expected result;
>>
>> tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
>> fchown05.c:44: TPASS: fchown(3, 700, 701), change owner/group ids passed
>> fchown05.c:44: TPASS: fchown(3, 702, -1), change owner id only passed
>> fchown05.c:44: TPASS: fchown(3, 703, 701), change owner id only passed
>> fchown05.c:44: TPASS: fchown(3, -1, 704), change group id only passed
>> fchown05.c:44: TPASS: fchown(3, 703, 705), change group id only passed
>> fchown05.c:44: TPASS: fchown(3, -1, -1), no change passed
> 
> Where do these tests reside? I'm not sure I know what LTP is. In any case,
> the patch should be correct as QEMU needs to differentiate between 32-bit
> and 64-bit SPARC.

I agree, it could be a side effect. I didn't check.

https://github.com/linux-test-project/ltp/releases/tag/20230127

Thanks,
Laurent