[PATCH 07/16] hw/i3c/aspeed_i3c: Use 32 bits on MMIO writes

[Joe Komlodi <komlodi@google.com>]

The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
---
 hw/i3c/aspeed_i3c.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 79715f462d..2ed09234ff 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -441,10 +441,11 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
 {
     AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque);
     uint32_t addr = offset >> 2;
+    uint32_t val32 = (uint32_t)value;
 
     trace_aspeed_i3c_device_write(s->id, offset, value);
 
-    value &= ~ast2600_i3c_device_ro[addr];
+    val32 &= ~ast2600_i3c_device_ro[addr];
     switch (addr) {
     case R_HW_CAPABILITY:
     case R_RESPONSE_QUEUE_PORT:
@@ -470,7 +471,7 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
     case R_RESET_CTRL:
         break;
     default:
-        s->regs[addr] = value;
+        s->regs[addr] = val32;
         break;
     }
 }
-- 
2.40.0.348.gf938b09366-goog