From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v3 2/6] target/riscv: Update cur_pmmask/base when xl changes
Date: Fri, 31 Mar 2023 09:45:26 +0800 [thread overview]
Message-ID: <20230331014530.29805-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230331014530.29805-1-liweiwei@iscas.ac.cn>
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/csr.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..43b9ad4500 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1277,8 +1277,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
}
env->mstatus = mstatus;
- env->xl = cpu_recompute_xl(env);
+ /*
+ * Except in debug mode, UXL/SXL can only be modified by higher
+ * privilege mode. So xl will not be changed in normal mode.
+ */
+ if (env->debugger) {
+ env->xl = cpu_recompute_xl(env);
+ riscv_cpu_update_mask(env);
+ }
return RISCV_EXCP_NONE;
}
--
2.25.1
next prev parent reply other threads:[~2023-03-31 1:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-31 1:45 [PATCH v3 0/6] target/riscv: Fix pointer mask related support Weiwei Li
2023-03-31 1:45 ` [PATCH v3 1/6] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-03-31 1:45 ` Weiwei Li [this message]
2023-03-31 1:45 ` [PATCH v3 3/6] target/riscv: Fix target address to update badaddr Weiwei Li
2023-03-31 1:45 ` [PATCH v3 4/6] target/riscv: Add support for PC-relative translation Weiwei Li
2023-03-31 1:45 ` [PATCH v3 5/6] target/riscv: Enable PC-relative translation in system mode Weiwei Li
2023-03-31 7:59 ` LIU Zhiwei
2023-03-31 1:45 ` [PATCH v3 6/6] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
-- strict thread matches above, loose matches on Subject: below --
2023-04-01 12:39 [PATCH v3 0/6] target/riscv: Fix pointer mask related support Weiwei Li
2023-04-01 12:39 ` [PATCH v3 2/6] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
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