qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v3 0/6] target/riscv: Fix pointer mask related support
@ 2023-03-31  1:45 Weiwei Li
  2023-03-31  1:45 ` [PATCH v3 1/6] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
                   ` (5 more replies)
  0 siblings, 6 replies; 9+ messages in thread
From: Weiwei Li @ 2023-03-31  1:45 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
	wangjunqiang, lazyparser, Weiwei Li

This patchset tries to fix some problem in current implementation for pointer mask, and add support for pointer mask of instruction fetch.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v2

v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
* Add patch 4 and 5 to use PC-relative translation for pointer mask for instruction fetch

v3:
* use target_pc temp instead of cpu_pc to store into badaddr in patch 3
* use dest_gpr instead of tcg_temp_new() for succ_pc in patch 4
* enable CF_PCREL for system mode in seperate patch 5

Weiwei Li (6):
  target/riscv: Fix pointer mask transformation for vector address
  target/riscv: Update cur_pmmask/base when xl changes
  target/riscv: Fix target address to update badaddr
  target/riscv: Add support for PC-relative translation
  target/riscv: Enable PC-relative translation in system mode
  target/riscv: Add pointer mask support for instruction fetch

 target/riscv/cpu.c                      | 31 +++++++----
 target/riscv/cpu.h                      |  1 +
 target/riscv/cpu_helper.c               | 20 ++++++-
 target/riscv/csr.c                      | 11 +++-
 target/riscv/insn_trans/trans_rvi.c.inc | 38 ++++++++++---
 target/riscv/translate.c                | 73 +++++++++++++++++++------
 target/riscv/vector_helper.c            |  2 +-
 7 files changed, 135 insertions(+), 41 deletions(-)

-- 
2.25.1



^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH v3 0/6] target/riscv: Fix pointer mask related support
@ 2023-04-01 12:39 Weiwei Li
  2023-04-01 12:39 ` [PATCH v3 3/6] target/riscv: Fix target address to update badaddr Weiwei Li
  0 siblings, 1 reply; 9+ messages in thread
From: Weiwei Li @ 2023-04-01 12:39 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
	wangjunqiang, lazyparser, Weiwei Li

This patchset tries to fix some problem in current implementation for pointer mask, and add support for pointer mask of instruction fetch.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v5

v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
* Add patch 4 and 5 to use PC-relative translation for pointer mask for instruction fetch

v3:
* use target_pc temp instead of cpu_pc to store into badaddr in patch 3
* use dest_gpr instead of tcg_temp_new() for succ_pc in patch 4
* enable CF_PCREL for system mode in seperate patch 5

v4：
* Fix wrong pc_save value for conditional jump in patch 4
* Fix tcg_cflags overwrite problem to make CF_PCREL really work in new patch 5
* Fix tb mis-matched problem in new patch 6

v5:
* use gen_get_target_pc to compute target address of auipc and successor address of jalr in patch 4.
* separate tcg related fix patches(5, 6) from this patchset

Weiwei Li (6):
  target/riscv: Fix pointer mask transformation for vector address
  target/riscv: Update cur_pmmask/base when xl changes
  target/riscv: Fix target address to update badaddr
  target/riscv: Add support for PC-relative translation
  target/riscv: Enable PC-relative translation in system mode
  target/riscv: Add pointer mask support for instruction fetch

 target/riscv/cpu.c                      | 31 +++++++----
 target/riscv/cpu.h                      |  1 +
 target/riscv/cpu_helper.c               | 20 ++++++-
 target/riscv/csr.c                      | 11 ++--
 target/riscv/insn_trans/trans_rvi.c.inc | 37 +++++++++----
 target/riscv/translate.c                | 72 ++++++++++++++++++-------
 target/riscv/vector_helper.c            |  2 +-
 7 files changed, 131 insertions(+), 43 deletions(-)

-- 
2.25.1



^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-04-01 12:41 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-31  1:45 [PATCH v3 0/6] target/riscv: Fix pointer mask related support Weiwei Li
2023-03-31  1:45 ` [PATCH v3 1/6] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-03-31  1:45 ` [PATCH v3 2/6] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
2023-03-31  1:45 ` [PATCH v3 3/6] target/riscv: Fix target address to update badaddr Weiwei Li
2023-03-31  1:45 ` [PATCH v3 4/6] target/riscv: Add support for PC-relative translation Weiwei Li
2023-03-31  1:45 ` [PATCH v3 5/6] target/riscv: Enable PC-relative translation in system mode Weiwei Li
2023-03-31  7:59   ` LIU Zhiwei
2023-03-31  1:45 ` [PATCH v3 6/6] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
  -- strict thread matches above, loose matches on Subject: below --
2023-04-01 12:39 [PATCH v3 0/6] target/riscv: Fix pointer mask related support Weiwei Li
2023-04-01 12:39 ` [PATCH v3 3/6] target/riscv: Fix target address to update badaddr Weiwei Li

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).