From: Mostafa Saleh <smostafa@google.com>
To: qemu-devel@nongnu.org
Cc: jean-philippe@linaro.org, eric.auger@redhat.com,
peter.maydell@linaro.org, qemu-arm@nongnu.org,
richard.henderson@linaro.org,
Mostafa Saleh <smostafa@google.com>
Subject: [RFC PATCH v3 02/10] hw/arm/smmuv3: Update translation config to hold stage-2
Date: Sat, 1 Apr 2023 10:49:45 +0000 [thread overview]
Message-ID: <20230401104953.1325983-3-smostafa@google.com> (raw)
In-Reply-To: <20230401104953.1325983-1-smostafa@google.com>
In preparation for adding stage-2 support, add a S2 config
struct(SMMUS2Cfg), composed of the following fields and embedded in
the main SMMUTransCfg:
-tsz: Size of IPA input region (S2T0SZ)
-sl0: Start level of translation (S2SL0)
-affd: AF Fault Disable (S2AFFD)
-record_faults: Record fault events (S2R)
-granule_sz: Granule page shift (based on S2TG)
-vmid: Virtual Machine ID (S2VMID)
-vttb: Address of translation table base (S2TTB)
-eff_ps: Effective PA output range (based on S2PS)
They will be used in the next patches in stage-2 address translation.
The fields in SMMUS2Cfg, are reordered to make the shared and stage-1
fields next to each other, this reordering didn't change the struct
size (104 bytes before and after).
Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas.
oas is stage-1 output address size. However, it is used to check
input address in case stage-1 is unimplemented or bypassed according
to SMMUv3 manual IHI0070.E "3.4. Address sizes"
Shared fields: stage, disabled, bypassed, aborted, iotlb_*.
No functional change intended.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
Changes in v3:
-Add record_faults for stage-2
-Reorder and document fields in SMMUTransCfg based on stage
-Rename oas in SMMUS2Cfg to eff_ps
-Improve comments in SMMUS2Cfg
Changes in v2:
-Add oas
---
include/hw/arm/smmu-common.h | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 9fcff26357..9cf3f37929 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -58,25 +58,41 @@ typedef struct SMMUTLBEntry {
uint8_t granule;
} SMMUTLBEntry;
+/* Stage-2 configuration. */
+typedef struct SMMUS2Cfg {
+ uint8_t tsz; /* Size of IPA input region (S2T0SZ) */
+ uint8_t sl0; /* Start level of translation (S2SL0) */
+ bool affd; /* AF Fault Disable (S2AFFD) */
+ bool record_faults; /* Record fault events (S2R) */
+ uint8_t granule_sz; /* Granule page shift (based on S2TG) */
+ uint8_t eff_ps; /* Effective PA output range (based on S2PS) */
+ uint16_t vmid; /* Virtual Machine ID (S2VMID) */
+ uint64_t vttb; /* Address of translation table base (S2TTB) */
+} SMMUS2Cfg;
+
/*
* Generic structure populated by derived SMMU devices
* after decoding the configuration information and used as
* input to the page table walk
*/
typedef struct SMMUTransCfg {
+ /* Shared fields between stage-1 and stage-2. */
int stage; /* translation stage */
- bool aa64; /* arch64 or aarch32 translation table */
bool disabled; /* smmu is disabled */
bool bypassed; /* translation is bypassed */
bool aborted; /* translation is aborted */
+ uint32_t iotlb_hits; /* counts IOTLB hits */
+ uint32_t iotlb_misses; /* counts IOTLB misses*/
+ /* Used by stage-1 only. */
+ bool aa64; /* arch64 or aarch32 translation table */
bool record_faults; /* record fault events */
uint64_t ttb; /* TT base address */
uint8_t oas; /* output address width */
uint8_t tbi; /* Top Byte Ignore */
uint16_t asid;
SMMUTransTableInfo tt[2];
- uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
- uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
+ /* Used by stage-2 only. */
+ struct SMMUS2Cfg s2cfg;
} SMMUTransCfg;
typedef struct SMMUDevice {
--
2.40.0.348.gf938b09366-goog
next prev parent reply other threads:[~2023-04-01 10:51 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-01 10:49 [RFC PATCH v3 00/10] Add stage-2 translation for SMMUv3 Mostafa Saleh
2023-04-01 10:49 ` [RFC PATCH v3 01/10] hw/arm/smmuv3: Add missing fields for IDR0 Mostafa Saleh
2023-04-01 10:49 ` Mostafa Saleh [this message]
2023-05-15 8:37 ` [RFC PATCH v3 02/10] hw/arm/smmuv3: Update translation config to hold stage-2 Eric Auger
2023-04-01 10:49 ` [RFC PATCH v3 03/10] hw/arm/smmuv3: Refactor stage-1 PTW Mostafa Saleh
2023-04-01 10:49 ` [RFC PATCH v3 04/10] hw/arm/smmuv3: Add page table walk for stage-2 Mostafa Saleh
2023-05-15 8:37 ` Eric Auger
2023-04-01 10:49 ` [RFC PATCH v3 05/10] hw/arm/smmuv3: Parse STE config " Mostafa Saleh
2023-05-15 13:03 ` Eric Auger
2023-05-15 15:37 ` Mostafa Saleh
2023-05-16 17:19 ` Eric Auger
2023-04-01 10:49 ` [RFC PATCH v3 06/10] hw/arm/smmuv3: Make TLB lookup work " Mostafa Saleh
2023-04-01 10:49 ` [RFC PATCH v3 07/10] hw/arm/smmuv3: Add VMID to TLB tagging Mostafa Saleh
2023-04-01 10:49 ` [RFC PATCH v3 08/10] hw/arm/smmuv3: Add CMDs related to stage-2 Mostafa Saleh
2023-05-15 13:17 ` Eric Auger
2023-05-15 14:14 ` Eric Auger
2023-05-15 15:32 ` Mostafa Saleh
2023-05-16 17:04 ` Eric Auger
2023-05-16 19:32 ` Mostafa Saleh
2023-04-01 10:49 ` [RFC PATCH v3 09/10] hw/arm/smmuv3: Add stage-2 support in iova notifier Mostafa Saleh
2023-04-01 10:49 ` [RFC PATCH v3 10/10] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Mostafa Saleh
2023-05-15 13:15 ` Eric Auger
2023-05-12 14:46 ` [RFC PATCH v3 00/10] Add stage-2 translation for SMMUv3 Peter Maydell
2023-05-12 15:26 ` Eric Auger
2023-05-15 13:03 ` Mostafa Saleh
2023-05-15 14:34 ` Eric Auger
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