From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
qemu-riscv@nongnu.org, qemu-ppc@nongnu.org
Subject: [PATCH 17/42] tcg: Introduce tcg_out_xchg
Date: Fri, 7 Apr 2023 19:42:49 -0700 [thread overview]
Message-ID: <20230408024314.3357414-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org>
We will want a backend interface for register swapping.
This is only properly defined for x86; all others get a
stub version that always indicates failure.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 2 ++
tcg/aarch64/tcg-target.c.inc | 5 +++++
tcg/arm/tcg-target.c.inc | 5 +++++
tcg/i386/tcg-target.c.inc | 8 ++++++++
tcg/loongarch64/tcg-target.c.inc | 5 +++++
tcg/mips/tcg-target.c.inc | 5 +++++
tcg/ppc/tcg-target.c.inc | 5 +++++
tcg/riscv/tcg-target.c.inc | 5 +++++
tcg/s390x/tcg-target.c.inc | 5 +++++
tcg/sparc64/tcg-target.c.inc | 5 +++++
tcg/tci/tcg-target.c.inc | 5 +++++
11 files changed, 55 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 6fe7dd6564..d82d99e1b0 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -115,6 +115,8 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+ __attribute__((unused));
static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
static void tcg_out_goto_tb(TCGContext *s, int which);
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 29bc97ed1c..4ec3cf3172 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1106,6 +1106,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_out_insn(s, 3305, LDR, 0, rd);
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index f865294861..4a5d57a41c 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2607,6 +2607,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out_movi32(s, COND_AL, ret, arg);
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 2d7c173a03..7d6bf30747 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -460,6 +460,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
+#define OPC_XCHG_EvGv (0x87)
#define OPC_GRP3_Eb (0xf6)
#define OPC_GRP3_Ev (0xf7)
@@ -1078,6 +1079,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
}
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
+ tcg_out_modrm(s, OPC_XCHG_EvGv + rexw, r1, r2);
+ return true;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index fc98b9b31b..0940788c6f 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -419,6 +419,11 @@ static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd,
}
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index f103cdb4e6..a83ebe8729 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -597,6 +597,11 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
tcg_out_ext32s(s, rd, rs);
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 612ad15bda..d3e547998f 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1153,6 +1153,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
}
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 081782d8c6..266fe1433d 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -561,6 +561,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 0578fce4d7..b399798664 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -1076,6 +1076,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
return false;
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 99ba0fdc2b..086981f097 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -542,6 +542,11 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
tcg_out_mov(s, TCG_TYPE_I32, rd, rs);
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 68531e35ec..4cf03a579c 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -645,6 +645,11 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
tcg_out_mov(s, TCG_TYPE_I32, rd, rs);
}
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
+{
+ return false;
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
--
2.34.1
next prev parent reply other threads:[~2023-04-08 2:51 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-08 2:42 [PATCH for-8.1 00/42] tcg: Simplify calls to load/store helpers Richard Henderson
2023-04-08 2:42 ` [PATCH for-8.0] tcg/i386: Adjust assert in tcg_out_addi_ptr Richard Henderson
2023-04-08 2:42 ` [PATCH 01/42] tcg: Replace if + tcg_abort with tcg_debug_assert Richard Henderson
2023-04-11 10:52 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 02/42] tcg: Replace tcg_abort with g_assert_not_reached Richard Henderson
2023-04-11 10:53 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 03/42] tcg: Split out tcg_out_ext8s Richard Henderson
2023-04-21 21:45 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 04/42] tcg: Split out tcg_out_ext8u Richard Henderson
2023-04-21 21:50 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 05/42] tcg: Split out tcg_out_ext16s Richard Henderson
2023-04-21 21:53 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 06/42] tcg: Split out tcg_out_ext16u Richard Henderson
2023-04-21 22:03 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 07/42] tcg: Split out tcg_out_ext32s Richard Henderson
2023-04-08 2:42 ` [PATCH 08/42] tcg: Split out tcg_out_ext32u Richard Henderson
2023-04-08 2:42 ` [PATCH 09/42] tcg: Split out tcg_out_exts_i32_i64 Richard Henderson
2023-04-08 2:42 ` [PATCH 10/42] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-04-08 2:42 ` [PATCH 11/42] tcg/mips: " Richard Henderson
2023-04-08 2:42 ` [PATCH 12/42] tcg/riscv: " Richard Henderson
2023-04-08 2:42 ` [PATCH 13/42] tcg: Split out tcg_out_extu_i32_i64 Richard Henderson
2023-04-08 2:42 ` [PATCH 14/42] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-04-08 2:42 ` [PATCH 15/42] tcg: Split out tcg_out_extrl_i64_i32 Richard Henderson
2023-04-08 2:42 ` [PATCH 16/42] tcg: Introduce tcg_out_movext Richard Henderson
2023-04-08 2:42 ` Richard Henderson [this message]
2023-04-08 2:42 ` [PATCH 18/42] tcg: Introduce tcg_out_movext2 Richard Henderson
2023-04-08 2:42 ` [PATCH 19/42] tcg: Clear TCGLabelQemuLdst on allocation Richard Henderson
2023-04-11 12:10 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 20/42] tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st} Richard Henderson
2023-04-11 12:12 ` Philippe Mathieu-Daudé
2023-04-12 11:51 ` Richard Henderson
2023-04-08 2:42 ` [PATCH 21/42] tcg/aarch64: Rename ext to d_type in tcg_out_qemu_ld Richard Henderson
2023-04-11 12:14 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 22/42] tcg/aarch64: Pass TGType to tcg_out_qemu_st Richard Henderson
2023-04-08 2:42 ` [PATCH 23/42] tcg/arm: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st} Richard Henderson
2023-04-08 2:42 ` [PATCH 24/42] tcg/i386: " Richard Henderson
2023-04-11 12:17 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 25/42] tcg/ppc: " Richard Henderson
2023-04-11 12:18 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 26/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-11 12:20 ` Philippe Mathieu-Daudé
2023-04-08 2:42 ` [PATCH 27/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2023-04-08 2:43 ` [PATCH 28/42] tcg/riscv: Expand arguments to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-08 2:43 ` [PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-04-08 2:43 ` [PATCH 30/42] tcg: Introduce tcg_out_ld_helper_args Richard Henderson
2023-04-08 2:43 ` [PATCH 31/42] tcg: Introduce tcg_out_st_helper_args Richard Henderson
2023-04-08 2:43 ` [PATCH 32/42] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08 2:43 ` [PATCH 33/42] tcg/mips: Reorg tcg_out_tlb_load Richard Henderson
2023-04-08 2:43 ` [PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08 2:43 ` [PATCH 35/42] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-04-08 2:43 ` [PATCH 36/42] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-04-08 2:43 ` [PATCH 37/42] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-04-08 2:43 ` [PATCH 38/42] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08 2:43 ` [PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Richard Henderson
2023-04-08 2:43 ` [PATCH 40/42] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08 2:43 ` [PATCH 41/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-04-08 2:43 ` [PATCH 42/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
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