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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
	qemu-riscv@nongnu.org, qemu-ppc@nongnu.org
Subject: [PATCH 36/42] tcg/ppc: Adjust constraints on qemu_ld/st
Date: Fri,  7 Apr 2023 19:43:08 -0700	[thread overview]
Message-ID: <20230408024314.3357414-38-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org>

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
available registers.  Now that we handle overlap betwen inputs and
helper arguments, we can allow any allocatable reg.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-set.h | 11 ++++-------
 tcg/ppc/tcg-target-con-str.h |  2 --
 tcg/ppc/tcg-target.c.inc     | 32 ++++++++++----------------------
 3 files changed, 14 insertions(+), 31 deletions(-)

diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
index a1a345883d..f206b29205 100644
--- a/tcg/ppc/tcg-target-con-set.h
+++ b/tcg/ppc/tcg-target-con-set.h
@@ -12,18 +12,15 @@
 C_O0_I1(r)
 C_O0_I2(r, r)
 C_O0_I2(r, ri)
-C_O0_I2(S, S)
 C_O0_I2(v, r)
-C_O0_I3(S, S, S)
+C_O0_I3(r, r, r)
 C_O0_I4(r, r, ri, ri)
-C_O0_I4(S, S, S, S)
-C_O1_I1(r, L)
+C_O0_I4(r, r, r, r)
 C_O1_I1(r, r)
 C_O1_I1(v, r)
 C_O1_I1(v, v)
 C_O1_I1(v, vr)
 C_O1_I2(r, 0, rZ)
-C_O1_I2(r, L, L)
 C_O1_I2(r, rI, ri)
 C_O1_I2(r, rI, rT)
 C_O1_I2(r, r, r)
@@ -36,7 +33,7 @@ C_O1_I2(v, v, v)
 C_O1_I3(v, v, v, v)
 C_O1_I4(r, r, ri, rZ, rZ)
 C_O1_I4(r, r, r, ri, ri)
-C_O2_I1(L, L, L)
-C_O2_I2(L, L, L, L)
+C_O2_I1(r, r, r)
+C_O2_I2(r, r, r, r)
 C_O2_I4(r, r, rI, rZM, r, r)
 C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
index 298ca20d5b..f3bf030bc3 100644
--- a/tcg/ppc/tcg-target-con-str.h
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3)
 REGS('B', 1u << TCG_REG_R4)
 REGS('C', 1u << TCG_REG_R5)
 REGS('D', 1u << TCG_REG_R6)
-REGS('L', ALL_QLOAD_REGS)
-REGS('S', ALL_QSTORE_REGS)
 
 /*
  * Define constraint letters for constants:
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 7195c0b817..dc4e88db8e 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -93,18 +93,6 @@
 #define ALL_GENERAL_REGS  0xffffffffu
 #define ALL_VECTOR_REGS   0xffffffff00000000ull
 
-#ifdef CONFIG_SOFTMMU
-#define ALL_QLOAD_REGS \
-    (ALL_GENERAL_REGS & \
-     ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
-#define ALL_QSTORE_REGS \
-    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
-                          (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
-#else
-#define ALL_QLOAD_REGS  (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
-#define ALL_QSTORE_REGS ALL_QLOAD_REGS
-#endif
-
 TCGPowerISA have_isa;
 static bool have_isel;
 bool have_altivec;
@@ -3780,23 +3768,23 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_qemu_ld_i32:
         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
-                ? C_O1_I1(r, L)
-                : C_O1_I2(r, L, L));
+                ? C_O1_I1(r, r)
+                : C_O1_I2(r, r, r));
 
     case INDEX_op_qemu_st_i32:
         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
-                ? C_O0_I2(S, S)
-                : C_O0_I3(S, S, S));
+                ? C_O0_I2(r, r)
+                : C_O0_I3(r, r, r));
 
     case INDEX_op_qemu_ld_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
-                : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
-                : C_O2_I2(L, L, L, L));
+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
+                : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, r)
+                : C_O2_I2(r, r, r, r));
 
     case INDEX_op_qemu_st_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
-                : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
-                : C_O0_I4(S, S, S, S));
+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
+                : TARGET_LONG_BITS == 32 ? C_O0_I3(r, r, r)
+                : C_O0_I4(r, r, r, r));
 
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
-- 
2.34.1



  parent reply	other threads:[~2023-04-08  2:52 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-08  2:42 [PATCH for-8.1 00/42] tcg: Simplify calls to load/store helpers Richard Henderson
2023-04-08  2:42 ` [PATCH for-8.0] tcg/i386: Adjust assert in tcg_out_addi_ptr Richard Henderson
2023-04-08  2:42 ` [PATCH 01/42] tcg: Replace if + tcg_abort with tcg_debug_assert Richard Henderson
2023-04-11 10:52   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 02/42] tcg: Replace tcg_abort with g_assert_not_reached Richard Henderson
2023-04-11 10:53   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 03/42] tcg: Split out tcg_out_ext8s Richard Henderson
2023-04-21 21:45   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 04/42] tcg: Split out tcg_out_ext8u Richard Henderson
2023-04-21 21:50   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 05/42] tcg: Split out tcg_out_ext16s Richard Henderson
2023-04-21 21:53   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 06/42] tcg: Split out tcg_out_ext16u Richard Henderson
2023-04-21 22:03   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 07/42] tcg: Split out tcg_out_ext32s Richard Henderson
2023-04-08  2:42 ` [PATCH 08/42] tcg: Split out tcg_out_ext32u Richard Henderson
2023-04-08  2:42 ` [PATCH 09/42] tcg: Split out tcg_out_exts_i32_i64 Richard Henderson
2023-04-08  2:42 ` [PATCH 10/42] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-04-08  2:42 ` [PATCH 11/42] tcg/mips: " Richard Henderson
2023-04-08  2:42 ` [PATCH 12/42] tcg/riscv: " Richard Henderson
2023-04-08  2:42 ` [PATCH 13/42] tcg: Split out tcg_out_extu_i32_i64 Richard Henderson
2023-04-08  2:42 ` [PATCH 14/42] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-04-08  2:42 ` [PATCH 15/42] tcg: Split out tcg_out_extrl_i64_i32 Richard Henderson
2023-04-08  2:42 ` [PATCH 16/42] tcg: Introduce tcg_out_movext Richard Henderson
2023-04-08  2:42 ` [PATCH 17/42] tcg: Introduce tcg_out_xchg Richard Henderson
2023-04-08  2:42 ` [PATCH 18/42] tcg: Introduce tcg_out_movext2 Richard Henderson
2023-04-08  2:42 ` [PATCH 19/42] tcg: Clear TCGLabelQemuLdst on allocation Richard Henderson
2023-04-11 12:10   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 20/42] tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st} Richard Henderson
2023-04-11 12:12   ` Philippe Mathieu-Daudé
2023-04-12 11:51     ` Richard Henderson
2023-04-08  2:42 ` [PATCH 21/42] tcg/aarch64: Rename ext to d_type in tcg_out_qemu_ld Richard Henderson
2023-04-11 12:14   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 22/42] tcg/aarch64: Pass TGType to tcg_out_qemu_st Richard Henderson
2023-04-08  2:42 ` [PATCH 23/42] tcg/arm: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st} Richard Henderson
2023-04-08  2:42 ` [PATCH 24/42] tcg/i386: " Richard Henderson
2023-04-11 12:17   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 25/42] tcg/ppc: " Richard Henderson
2023-04-11 12:18   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 26/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-11 12:20   ` Philippe Mathieu-Daudé
2023-04-08  2:42 ` [PATCH 27/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2023-04-08  2:43 ` [PATCH 28/42] tcg/riscv: Expand arguments to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-08  2:43 ` [PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-04-08  2:43 ` [PATCH 30/42] tcg: Introduce tcg_out_ld_helper_args Richard Henderson
2023-04-08  2:43 ` [PATCH 31/42] tcg: Introduce tcg_out_st_helper_args Richard Henderson
2023-04-08  2:43 ` [PATCH 32/42] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08  2:43 ` [PATCH 33/42] tcg/mips: Reorg tcg_out_tlb_load Richard Henderson
2023-04-08  2:43 ` [PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08  2:43 ` [PATCH 35/42] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-04-08  2:43 ` Richard Henderson [this message]
2023-04-08  2:43 ` [PATCH 37/42] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-04-08  2:43 ` [PATCH 38/42] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08  2:43 ` [PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Richard Henderson
2023-04-08  2:43 ` [PATCH 40/42] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-08  2:43 ` [PATCH 41/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-04-08  2:43 ` [PATCH 42/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson

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