From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 2/7] target/riscv: Introduce cur_insn_len into DisasContext
Date: Sun, 9 Apr 2023 18:53:01 +0800 [thread overview]
Message-ID: <20230409105306.28575-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230409105306.28575-1-liweiwei@iscas.ac.cn>
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1c8eae86c5..eee13b1225 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,6 +59,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong cur_insn_len;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
@@ -1117,8 +1118,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
};
ctx->virt_inst_excp = false;
+ ctx->cur_insn_len = insn_len(opcode);
/* Check for compressed insn */
- if (insn_len(opcode) == 2) {
+ if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
--
2.25.1
next prev parent reply other threads:[~2023-04-09 10:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-09 10:52 [PATCH 0/7] target/riscv: Add support for PC-relative translation Weiwei Li
2023-04-09 10:53 ` [PATCH 1/7] target/riscv: Fix target address to update badaddr Weiwei Li
2023-04-09 10:53 ` Weiwei Li [this message]
2023-04-09 10:53 ` [PATCH 3/7] target/riscv: Change gen_goto_tb to work on displacements Weiwei Li
2023-04-09 10:53 ` [PATCH 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc Weiwei Li
2023-04-09 10:53 ` [PATCH 5/7] target/riscv: Use true diff for gen_pc_plus_diff Weiwei Li
2023-04-09 10:53 ` [PATCH 6/7] target/riscv: Enable PC-relative translation Weiwei Li
2023-04-09 10:53 ` [PATCH 7/7] target/riscv: Remove pc_succ_insn from DisasContext Weiwei Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230409105306.28575-3-liweiwei@iscas.ac.cn \
--to=liweiwei@iscas.ac.cn \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=lazyparser@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=wangjunqiang@iscas.ac.cn \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).