From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 5/7] target/riscv: Use true diff for gen_pc_plus_diff
Date: Sun, 9 Apr 2023 18:53:04 +0800 [thread overview]
Message-ID: <20230409105306.28575-6-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230409105306.28575-1-liweiwei@iscas.ac.cn>
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvi.c.inc | 6 ++----
target/riscv/translate.c | 13 ++++++-------
2 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 012534c883..b77e6c4fb6 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -158,7 +158,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
- target_ulong next_pc;
if (get_xl(ctx) == MXL_RV128) {
TCGv src1h = get_gprh(ctx, a->rs1);
@@ -175,11 +174,10 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
- next_pc = ctx->base.pc_next + a->imm;
- if (!has_ext(ctx, RVC) && (next_pc & 0x3)) {
+ if (!has_ext(ctx, RVC) && (a->imm & 0x3)) {
/* misaligned */
TCGv target_pc = tcg_temp_new();
- gen_pc_plus_diff(target_pc, ctx, next_pc);
+ gen_pc_plus_diff(target_pc, ctx, a->imm);
gen_exception_inst_addr_mis(ctx, target_pc);
} else {
gen_goto_tb(ctx, 0, a->imm);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index db061064a6..50a87d7367 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -224,8 +224,10 @@ static void decode_save_opc(DisasContext *ctx)
}
static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
- target_ulong dest)
+ target_long diff)
{
+ target_ulong dest = ctx->base.pc_next + diff;
+
if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
}
@@ -234,7 +236,7 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
static void gen_update_pc(DisasContext *ctx, target_long diff)
{
- gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
+ gen_pc_plus_diff(cpu_pc, ctx, diff);
}
static void generate_exception(DisasContext *ctx, int excp)
@@ -545,14 +547,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
- target_ulong next_pc;
-
/* check misaligned: */
- next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC)) {
- if ((next_pc & 0x3) != 0) {
+ if ((imm & 0x3) != 0) {
TCGv target_pc = tcg_temp_new();
- gen_pc_plus_diff(target_pc, ctx, next_pc);
+ gen_pc_plus_diff(target_pc, ctx, imm);
gen_exception_inst_addr_mis(ctx, target_pc);
return;
}
--
2.25.1
next prev parent reply other threads:[~2023-04-09 10:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-09 10:52 [PATCH 0/7] target/riscv: Add support for PC-relative translation Weiwei Li
2023-04-09 10:53 ` [PATCH 1/7] target/riscv: Fix target address to update badaddr Weiwei Li
2023-04-09 10:53 ` [PATCH 2/7] target/riscv: Introduce cur_insn_len into DisasContext Weiwei Li
2023-04-09 10:53 ` [PATCH 3/7] target/riscv: Change gen_goto_tb to work on displacements Weiwei Li
2023-04-09 10:53 ` [PATCH 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc Weiwei Li
2023-04-09 10:53 ` Weiwei Li [this message]
2023-04-09 10:53 ` [PATCH 6/7] target/riscv: Enable PC-relative translation Weiwei Li
2023-04-09 10:53 ` [PATCH 7/7] target/riscv: Remove pc_succ_insn from DisasContext Weiwei Li
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