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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Date: Mon, 10 Apr 2023 15:14:08 +0100	[thread overview]
Message-ID: <20230410141408.3564269-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230410141408.3564269-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

The guarded bit comes from the stage1 walk.

Fixes: Coverity CID 1507929
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 58a6de09bc9..6d72950a795 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2576,6 +2576,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
 
     assert(!s1.is_s2_format);
     ret.is_s2_format = false;
+    ret.guarded = s1.guarded;
 
     if (s1.attrs == 0xf0) {
         tagged = true;
-- 
2.34.1



  parent reply	other threads:[~2023-04-10 14:15 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-10 14:14 [PULL 0/2] target-arm queue Peter Maydell
2023-04-10 14:14 ` [PULL 1/2] target/arm: PTE bit GP only applies to stage1 Peter Maydell
2023-04-10 14:14 ` Peter Maydell [this message]
2023-04-10 18:45 ` [PULL 0/2] target-arm queue Peter Maydell

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