From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
qemu-riscv@nongnu.org, qemu-ppc@nongnu.org
Subject: [PATCH v2 15/54] tcg: Split out tcg_out_extrl_i64_i32
Date: Mon, 10 Apr 2023 18:04:33 -0700 [thread overview]
Message-ID: <20230411010512.5375-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org>
We will need a backend interface for type truncation. For those backends
that did not enable TCG_TARGET_HAS_extrl_i64_i32, use tcg_out_mov.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 4 ++++
tcg/aarch64/tcg-target.c.inc | 6 ++++++
tcg/arm/tcg-target.c.inc | 5 +++++
tcg/i386/tcg-target.c.inc | 9 ++++++---
tcg/loongarch64/tcg-target.c.inc | 10 ++++++----
tcg/mips/tcg-target.c.inc | 9 ++++++---
tcg/ppc/tcg-target.c.inc | 7 +++++++
tcg/riscv/tcg-target.c.inc | 10 ++++++----
tcg/s390x/tcg-target.c.inc | 6 ++++++
tcg/sparc64/tcg-target.c.inc | 9 ++++++---
tcg/tci/tcg-target.c.inc | 7 +++++++
11 files changed, 65 insertions(+), 17 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 17bd6d4581..0188152c37 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -113,6 +113,7 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg);
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
static void tcg_out_goto_tb(TCGContext *s, int which);
@@ -4537,6 +4538,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_extu_i32_i64:
tcg_out_extu_i32_i64(s, new_args[0], new_args[1]);
break;
+ case INDEX_op_extrl_i64_i32:
+ tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]);
+ break;
default:
if (def->flags & TCG_OPF_VECTOR) {
tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index ca8b25865b..bd1fab193e 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1467,6 +1467,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn)
tcg_out_ext32u(s, rd, rn);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+ tcg_out_mov(s, TCG_TYPE_I32, rd, rn);
+}
+
static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
TCGReg rn, int64_t aimm)
{
@@ -2337,6 +2342,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 2135616e12..1820655ee3 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1013,6 +1013,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn)
g_assert_not_reached();
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+ g_assert_not_reached();
+}
+
static void tcg_out_bswap16(TCGContext *s, ARMCond cond,
TCGReg rd, TCGReg rn, int flags)
{
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index a156929477..a166a195c4 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1311,6 +1311,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src)
}
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src)
+{
+ tcg_out_ext32u(s, dest, src);
+}
+
static inline void tcg_out_bswap64(TCGContext *s, int reg)
{
tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0);
@@ -2765,9 +2770,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0);
break;
- case INDEX_op_extrl_i64_i32:
- tcg_out_ext32u(s, a0, a1);
- break;
case INDEX_op_extrh_i64_i32:
tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32);
break;
@@ -2848,6 +2850,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index d83bd9de49..b0e076c462 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -468,6 +468,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
tcg_out_ext32u(s, ret, arg);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_ext32s(s, ret, arg);
+}
+
static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
TCGReg a0, TCGReg a1, TCGReg a2,
bool c2, bool is_32bit)
@@ -1258,10 +1263,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
break;
- case INDEX_op_extrl_i64_i32:
- tcg_out_ext32s(s, a0, a1);
- break;
-
case INDEX_op_extrh_i64_i32:
tcg_out_opc_srai_d(s, a0, a1, 32);
break;
@@ -1624,6 +1625,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 4789b0a40c..f103cdb4e6 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -592,6 +592,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
tcg_out_ext32u(s, rd, rs);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
+{
+ tcg_out_ext32s(s, rd, rs);
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
@@ -2306,9 +2311,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_extrh_i64_i32:
tcg_out_dsra(s, a0, a1, 32);
break;
- case INDEX_op_extrl_i64_i32:
- tcg_out_ext32s(s, a0, a1);
- break;
case INDEX_op_sar_i32:
i1 = OPC_SRAV, i2 = OPC_SRA;
@@ -2457,6 +2459,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index bd298c55fd..4c4178b700 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -817,6 +817,12 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src)
tcg_out_ext32u(s, dst, src);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ tcg_out_mov(s, TCG_TYPE_I32, rd, rn);
+}
+
static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
{
tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
@@ -3138,6 +3144,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index a6d352976c..6af5c25f02 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -614,6 +614,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
tcg_out_ext32u(s, ret, arg);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_ext32s(s, ret, arg);
+}
+
static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
TCGReg addr, intptr_t offset)
{
@@ -1609,10 +1614,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_qemu_st(s, args, true);
break;
- case INDEX_op_extrl_i64_i32:
- tcg_out_ext32s(s, a0, a1);
- break;
-
case INDEX_op_extrh_i64_i32:
tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
break;
@@ -1648,6 +1649,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index e17d000991..360229cdd3 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -1132,6 +1132,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src)
tcg_out_ext32u(s, dest, src);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src)
+{
+ tcg_out_mov(s, TCG_TYPE_I32, dest, src);
+}
+
static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
{
int msb, lsb;
@@ -2632,6 +2637,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index c57a8c8304..18ddd6bb9f 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -537,6 +537,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
tcg_out_ext32u(s, rd, rs);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
+{
+ tcg_out_mov(s, TCG_TYPE_I32, rd, rs);
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
@@ -1687,9 +1692,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_divu_i64:
c = ARITH_UDIVX;
goto gen_arith;
- case INDEX_op_extrl_i64_i32:
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- break;
case INDEX_op_extrh_i64_i32:
tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
break;
@@ -1744,6 +1746,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 48c9dbd0b4..68531e35ec 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -639,6 +639,12 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
tcg_out_ext32u(s, rd, rs);
}
+static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
+{
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ tcg_out_mov(s, TCG_TYPE_I32, rd, rs);
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
@@ -881,6 +887,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
--
2.34.1
next prev parent reply other threads:[~2023-04-11 1:08 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 1:04 [PATCH v2 00/54] tcg: Simplify calls to load/store helpers Richard Henderson
2023-04-11 1:04 ` [PATCH v2 01/54] tcg: Replace if + tcg_abort with tcg_debug_assert Richard Henderson
2023-04-21 22:11 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 02/54] tcg: Replace tcg_abort with g_assert_not_reached Richard Henderson
2023-04-21 22:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 03/54] tcg: Split out tcg_out_ext8s Richard Henderson
2023-04-21 22:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 04/54] tcg: Split out tcg_out_ext8u Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 05/54] tcg: Split out tcg_out_ext16s Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 06/54] tcg: Split out tcg_out_ext16u Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 07/54] tcg: Split out tcg_out_ext32s Richard Henderson
2023-04-21 22:38 ` Philippe Mathieu-Daudé
2023-04-21 22:42 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 08/54] tcg: Split out tcg_out_ext32u Richard Henderson
2023-04-21 22:40 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 09/54] tcg: Split out tcg_out_exts_i32_i64 Richard Henderson
2023-04-21 22:44 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 10/54] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 11/54] tcg/mips: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 12/54] tcg/riscv: " Richard Henderson
2023-04-12 20:01 ` Daniel Henrique Barboza
2023-04-11 1:04 ` [PATCH v2 13/54] tcg: Split out tcg_out_extu_i32_i64 Richard Henderson
2023-04-21 22:46 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 14/54] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-04-11 1:04 ` Richard Henderson [this message]
2023-04-21 22:48 ` [PATCH v2 15/54] tcg: Split out tcg_out_extrl_i64_i32 Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 16/54] tcg: Introduce tcg_out_movext Richard Henderson
2023-04-21 23:02 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 17/54] tcg: Introduce tcg_out_xchg Richard Henderson
2023-04-21 23:05 ` Philippe Mathieu-Daudé
2023-04-21 23:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 18/54] tcg: Introduce tcg_out_movext2 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 19/54] tcg: Clear TCGLabelQemuLdst on allocation Richard Henderson
2023-04-21 22:20 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:45 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-21 22:19 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:43 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 23/54] tcg/mips: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 24/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-11 1:04 ` [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 19:06 ` Daniel Henrique Barboza
2023-04-23 18:48 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 26/54] tcg/s390x: Pass TCGType " Richard Henderson
2023-04-21 22:15 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2023-04-12 20:18 ` Daniel Henrique Barboza
2023-04-13 7:12 ` Richard Henderson
2023-04-13 9:55 ` Daniel Henrique Barboza
2023-04-13 9:55 ` Daniel Henrique Barboza
2023-04-23 18:33 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 20:19 ` Daniel Henrique Barboza
2023-04-23 18:35 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 29/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-04-21 22:27 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 30/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-21 22:28 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 31/54] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-04-21 22:29 ` Philippe Mathieu-Daudé
2023-04-23 7:30 ` Richard Henderson
2023-04-11 1:04 ` [PATCH v2 32/54] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-04-23 18:50 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 33/54] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-04-23 18:55 ` Philippe Mathieu-Daudé
2023-04-24 4:36 ` Richard Henderson
2023-04-11 1:04 ` [PATCH v2 34/54] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-04-23 18:57 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 35/54] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-04-11 1:04 ` [PATCH v2 36/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 37/54] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 38/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 39/54] tcg/arm: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 40/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 41/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11 1:05 ` [PATCH v2 42/54] tcg/ppc: " Richard Henderson
2023-04-12 19:06 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 43/54] tcg/riscv: " Richard Henderson
2023-04-12 20:19 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 44/54] tcg/s390x: " Richard Henderson
2023-04-11 1:05 ` [PATCH v2 45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 46/54] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-04-11 1:05 ` [PATCH v2 47/54] tcg/mips: Reorg tcg_out_tlb_load Richard Henderson
2023-04-11 1:05 ` [PATCH v2 48/54] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 49/54] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 51/54] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-12 20:20 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 54/54] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
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