From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
qemu-riscv@nongnu.org, qemu-ppc@nongnu.org
Subject: [PATCH v2 18/54] tcg: Introduce tcg_out_movext2
Date: Mon, 10 Apr 2023 18:04:36 -0700 [thread overview]
Message-ID: <20230411010512.5375-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org>
This is common code in most qemu_{ld,st} slow paths, moving two
registers when there may be overlap between sources and destinations.
At present, this is only used by 32-bit hosts for 64-bit data,
but will shortly be used for more than that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 69 ++++++++++++++++++++++++++++++++++++---
tcg/arm/tcg-target.c.inc | 42 ++++++++++--------------
tcg/i386/tcg-target.c.inc | 19 +++++------
3 files changed, 89 insertions(+), 41 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index fde5ccc57c..cfd3262a4a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -115,8 +115,7 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg);
static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
-static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
- __attribute__((unused));
+static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2);
static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
static void tcg_out_goto_tb(TCGContext *s, int which);
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
@@ -354,6 +353,14 @@ void tcg_raise_tb_overflow(TCGContext *s)
siglongjmp(s->jmp_trans, -2);
}
+typedef struct TCGMovExtend {
+ TCGReg dst;
+ TCGReg src;
+ TCGType dst_type;
+ TCGType src_type;
+ MemOp src_ext;
+} TCGMovExtend;
+
/**
* tcg_out_movext -- move and extend
* @s: tcg context
@@ -365,9 +372,8 @@ void tcg_raise_tb_overflow(TCGContext *s)
*
* Move or extend @src into @dst, depending on @src_ext and the types.
*/
-static void __attribute__((unused))
-tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst,
- TCGType src_type, MemOp src_ext, TCGReg src)
+static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst,
+ TCGType src_type, MemOp src_ext, TCGReg src)
{
switch (src_ext) {
case MO_UB:
@@ -417,6 +423,59 @@ tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst,
}
}
+/* Minor variations on a theme, using a structure. */
+static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i,
+ TCGReg src)
+{
+ tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src);
+}
+
+static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i)
+{
+ tcg_out_movext1_new_src(s, i, i->src);
+}
+
+/**
+ * tcg_out_movext2 -- move and extend two pair
+ * @s: tcg context
+ * @i1: first move description
+ * @i2: second move description
+ * @scratch: temporary register, or -1 for none
+ *
+ * As tcg_out_movext, for both @i1 and @i2, caring for overlap
+ * between the sources and destinations.
+ */
+
+static void __attribute__((unused))
+tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1,
+ const TCGMovExtend *i2, int scratch)
+{
+ TCGReg src1 = i1->src;
+ TCGReg src2 = i2->src;
+
+ if (i1->dst != src2) {
+ tcg_out_movext1(s, i1);
+ tcg_out_movext1(s, i2);
+ return;
+ }
+ if (i2->dst == src1) {
+ TCGType src1_type = i1->src_type;
+ TCGType src2_type = i2->src_type;
+
+ if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) {
+ /* The data is now in the correct registers, now extend. */
+ src1 = i2->src;
+ src2 = i1->src;
+ } else {
+ tcg_debug_assert(scratch >= 0);
+ tcg_out_mov(s, src1_type, scratch, src1);
+ src1 = scratch;
+ }
+ }
+ tcg_out_movext1_new_src(s, i2, src2);
+ tcg_out_movext1_new_src(s, i1, src1);
+}
+
#define C_PFX1(P, A) P##A
#define C_PFX2(P, A, B) P##A##_##B
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 4a5d57a41c..83c818a58b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1545,7 +1545,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGReg argreg, datalo, datahi;
+ TCGReg argreg;
MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
@@ -1565,20 +1565,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
/* Use the canonical unsigned helpers and minimize icache usage. */
tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]);
- datalo = lb->datalo_reg;
- datahi = lb->datahi_reg;
if ((opc & MO_SIZE) == MO_64) {
- if (datalo != TCG_REG_R1) {
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
- tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
- } else if (datahi != TCG_REG_R0) {
- tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
- } else {
- tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0);
- tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP);
- }
+ TCGMovExtend ext[2] = {
+ { .dst = lb->datalo_reg, .dst_type = TCG_TYPE_I32,
+ .src = TCG_REG_R0, .src_type = TCG_TYPE_I32, .src_ext = MO_UL },
+ { .dst = lb->datahi_reg, .dst_type = TCG_TYPE_I32,
+ .src = TCG_REG_R1, .src_type = TCG_TYPE_I32, .src_ext = MO_UL },
+ };
+ tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP);
} else {
tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg,
TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0);
@@ -1663,17 +1657,15 @@ static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
if (TARGET_LONG_BITS == 64) {
/* 64-bit target address is aligned into R2:R3. */
- if (l->addrhi_reg != TCG_REG_R2) {
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg);
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg);
- } else if (l->addrlo_reg != TCG_REG_R3) {
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg);
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg);
- } else {
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2);
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3);
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1);
- }
+ TCGMovExtend ext[2] = {
+ { .dst = TCG_REG_R2, .dst_type = TCG_TYPE_I32,
+ .src = l->addrlo_reg,
+ .src_type = TCG_TYPE_I32, .src_ext = MO_UL },
+ { .dst = TCG_REG_R3, .dst_type = TCG_TYPE_I32,
+ .src = l->addrhi_reg,
+ .src_type = TCG_TYPE_I32, .src_ext = MO_UL },
+ };
+ tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP);
} else {
tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg);
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index ce87f8fbc9..238a75b17e 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1916,7 +1916,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
- TCGReg data_reg;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
/* resolve label address */
@@ -1953,18 +1952,16 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
- data_reg = l->datalo_reg;
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
- if (data_reg == TCG_REG_EDX) {
- /* xchg %edx, %eax */
- tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0);
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX);
- } else {
- tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX);
- }
+ TCGMovExtend ext[2] = {
+ { .dst = l->datalo_reg, .dst_type = TCG_TYPE_I32,
+ .src = TCG_REG_EAX, .src_type = TCG_TYPE_I32, .src_ext = MO_UL },
+ { .dst = l->datahi_reg, .dst_type = TCG_TYPE_I32,
+ .src = TCG_REG_EDX, .src_type = TCG_TYPE_I32, .src_ext = MO_UL },
+ };
+ tcg_out_movext2(s, &ext[0], &ext[1], -1);
} else {
- tcg_out_movext(s, l->type, data_reg,
+ tcg_out_movext(s, l->type, l->datalo_reg,
TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX);
}
--
2.34.1
next prev parent reply other threads:[~2023-04-11 1:11 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 1:04 [PATCH v2 00/54] tcg: Simplify calls to load/store helpers Richard Henderson
2023-04-11 1:04 ` [PATCH v2 01/54] tcg: Replace if + tcg_abort with tcg_debug_assert Richard Henderson
2023-04-21 22:11 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 02/54] tcg: Replace tcg_abort with g_assert_not_reached Richard Henderson
2023-04-21 22:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 03/54] tcg: Split out tcg_out_ext8s Richard Henderson
2023-04-21 22:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 04/54] tcg: Split out tcg_out_ext8u Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 05/54] tcg: Split out tcg_out_ext16s Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 06/54] tcg: Split out tcg_out_ext16u Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 07/54] tcg: Split out tcg_out_ext32s Richard Henderson
2023-04-21 22:38 ` Philippe Mathieu-Daudé
2023-04-21 22:42 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 08/54] tcg: Split out tcg_out_ext32u Richard Henderson
2023-04-21 22:40 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 09/54] tcg: Split out tcg_out_exts_i32_i64 Richard Henderson
2023-04-21 22:44 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 10/54] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 11/54] tcg/mips: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 12/54] tcg/riscv: " Richard Henderson
2023-04-12 20:01 ` Daniel Henrique Barboza
2023-04-11 1:04 ` [PATCH v2 13/54] tcg: Split out tcg_out_extu_i32_i64 Richard Henderson
2023-04-21 22:46 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 14/54] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 15/54] tcg: Split out tcg_out_extrl_i64_i32 Richard Henderson
2023-04-21 22:48 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 16/54] tcg: Introduce tcg_out_movext Richard Henderson
2023-04-21 23:02 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 17/54] tcg: Introduce tcg_out_xchg Richard Henderson
2023-04-21 23:05 ` Philippe Mathieu-Daudé
2023-04-21 23:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` Richard Henderson [this message]
2023-04-11 1:04 ` [PATCH v2 19/54] tcg: Clear TCGLabelQemuLdst on allocation Richard Henderson
2023-04-21 22:20 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:45 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-21 22:19 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:43 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 23/54] tcg/mips: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 24/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-11 1:04 ` [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 19:06 ` Daniel Henrique Barboza
2023-04-23 18:48 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 26/54] tcg/s390x: Pass TCGType " Richard Henderson
2023-04-21 22:15 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2023-04-12 20:18 ` Daniel Henrique Barboza
2023-04-13 7:12 ` Richard Henderson
2023-04-13 9:55 ` Daniel Henrique Barboza
2023-04-13 9:55 ` Daniel Henrique Barboza
2023-04-23 18:33 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 20:19 ` Daniel Henrique Barboza
2023-04-23 18:35 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 29/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-04-21 22:27 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 30/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-21 22:28 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 31/54] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-04-21 22:29 ` Philippe Mathieu-Daudé
2023-04-23 7:30 ` Richard Henderson
2023-04-11 1:04 ` [PATCH v2 32/54] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-04-23 18:50 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 33/54] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-04-23 18:55 ` Philippe Mathieu-Daudé
2023-04-24 4:36 ` Richard Henderson
2023-04-11 1:04 ` [PATCH v2 34/54] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-04-23 18:57 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 35/54] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-04-11 1:04 ` [PATCH v2 36/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 37/54] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 38/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 39/54] tcg/arm: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 40/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 41/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11 1:05 ` [PATCH v2 42/54] tcg/ppc: " Richard Henderson
2023-04-12 19:06 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 43/54] tcg/riscv: " Richard Henderson
2023-04-12 20:19 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 44/54] tcg/s390x: " Richard Henderson
2023-04-11 1:05 ` [PATCH v2 45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 46/54] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-04-11 1:05 ` [PATCH v2 47/54] tcg/mips: Reorg tcg_out_tlb_load Richard Henderson
2023-04-11 1:05 ` [PATCH v2 48/54] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 49/54] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 51/54] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-12 20:20 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 54/54] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
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