qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
	qemu-riscv@nongnu.org, qemu-ppc@nongnu.org
Subject: [PATCH v2 21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st}
Date: Mon, 10 Apr 2023 18:04:39 -0700	[thread overview]
Message-ID: <20230411010512.5375-22-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org>

Mark the argument registers const, because they must be passed to
add_qemu_ldst_label unmodified.  Rename the 'ext' parameter 'data_type' to
make the use clearer; pass it to tcg_out_qemu_st as well to even out the
interfaces.  Rename the 'otype' local 'addr_type' to make the use clearer.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.c.inc | 42 ++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 4ec3cf3172..251464ae6f 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1850,23 +1850,23 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
     }
 }
 
-static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
-                            MemOpIdx oi, TCGType ext)
+static void tcg_out_qemu_ld(TCGContext *s, const TCGReg data_reg,
+                            const TCGReg addr_reg, const MemOpIdx oi,
+                            TCGType data_type)
 {
     MemOp memop = get_memop(oi);
-    const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+    TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
 
     /* Byte swapping is left to middle-end expansion. */
     tcg_debug_assert((memop & MO_BSWAP) == 0);
 
 #ifdef CONFIG_SOFTMMU
-    unsigned mem_index = get_mmuidx(oi);
     tcg_insn_unit *label_ptr;
 
-    tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
-    tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
-                           TCG_REG_X1, otype, addr_reg);
-    add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
+    tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1);
+    tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
+                           TCG_REG_X1, addr_type, addr_reg);
+    add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
                         s->code_ptr, label_ptr);
 #else /* !CONFIG_SOFTMMU */
     unsigned a_bits = get_alignment_bits(memop);
@@ -1874,33 +1874,33 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
         tcg_out_test_alignment(s, true, addr_reg, a_bits);
     }
     if (USE_GUEST_BASE) {
-        tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
-                               TCG_REG_GUEST_BASE, otype, addr_reg);
+        tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
+                               TCG_REG_GUEST_BASE, addr_type, addr_reg);
     } else {
-        tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+        tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
                                addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
     }
 #endif /* CONFIG_SOFTMMU */
 }
 
-static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
-                            MemOpIdx oi)
+static void tcg_out_qemu_st(TCGContext *s, const TCGReg data_reg,
+                            const TCGReg addr_reg, const MemOpIdx oi,
+                            TCGType data_type)
 {
     MemOp memop = get_memop(oi);
-    const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+    TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
 
     /* Byte swapping is left to middle-end expansion. */
     tcg_debug_assert((memop & MO_BSWAP) == 0);
 
 #ifdef CONFIG_SOFTMMU
-    unsigned mem_index = get_mmuidx(oi);
     tcg_insn_unit *label_ptr;
 
-    tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
+    tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0);
     tcg_out_qemu_st_direct(s, memop, data_reg,
-                           TCG_REG_X1, otype, addr_reg);
-    add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
-                        data_reg, addr_reg, s->code_ptr, label_ptr);
+                           TCG_REG_X1, addr_type, addr_reg);
+    add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
+                        s->code_ptr, label_ptr);
 #else /* !CONFIG_SOFTMMU */
     unsigned a_bits = get_alignment_bits(memop);
     if (a_bits) {
@@ -1908,7 +1908,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
     }
     if (USE_GUEST_BASE) {
         tcg_out_qemu_st_direct(s, memop, data_reg,
-                               TCG_REG_GUEST_BASE, otype, addr_reg);
+                               TCG_REG_GUEST_BASE, addr_type, addr_reg);
     } else {
         tcg_out_qemu_st_direct(s, memop, data_reg,
                                addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
@@ -2249,7 +2249,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         break;
     case INDEX_op_qemu_st_i32:
     case INDEX_op_qemu_st_i64:
-        tcg_out_qemu_st(s, REG0(0), a1, a2);
+        tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
         break;
 
     case INDEX_op_bswap64_i64:
-- 
2.34.1



  parent reply	other threads:[~2023-04-11  1:19 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-11  1:04 [PATCH v2 00/54] tcg: Simplify calls to load/store helpers Richard Henderson
2023-04-11  1:04 ` [PATCH v2 01/54] tcg: Replace if + tcg_abort with tcg_debug_assert Richard Henderson
2023-04-21 22:11   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 02/54] tcg: Replace tcg_abort with g_assert_not_reached Richard Henderson
2023-04-21 22:08   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 03/54] tcg: Split out tcg_out_ext8s Richard Henderson
2023-04-21 22:08   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 04/54] tcg: Split out tcg_out_ext8u Richard Henderson
2023-04-21 22:09   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 05/54] tcg: Split out tcg_out_ext16s Richard Henderson
2023-04-21 22:09   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 06/54] tcg: Split out tcg_out_ext16u Richard Henderson
2023-04-21 22:09   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 07/54] tcg: Split out tcg_out_ext32s Richard Henderson
2023-04-21 22:38   ` Philippe Mathieu-Daudé
2023-04-21 22:42     ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 08/54] tcg: Split out tcg_out_ext32u Richard Henderson
2023-04-21 22:40   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 09/54] tcg: Split out tcg_out_exts_i32_i64 Richard Henderson
2023-04-21 22:44   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 10/54] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-04-11  1:04 ` [PATCH v2 11/54] tcg/mips: " Richard Henderson
2023-04-11  1:04 ` [PATCH v2 12/54] tcg/riscv: " Richard Henderson
2023-04-12 20:01   ` Daniel Henrique Barboza
2023-04-11  1:04 ` [PATCH v2 13/54] tcg: Split out tcg_out_extu_i32_i64 Richard Henderson
2023-04-21 22:46   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 14/54] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-04-11  1:04 ` [PATCH v2 15/54] tcg: Split out tcg_out_extrl_i64_i32 Richard Henderson
2023-04-21 22:48   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 16/54] tcg: Introduce tcg_out_movext Richard Henderson
2023-04-21 23:02   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 17/54] tcg: Introduce tcg_out_xchg Richard Henderson
2023-04-21 23:05   ` Philippe Mathieu-Daudé
2023-04-21 23:08     ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 18/54] tcg: Introduce tcg_out_movext2 Richard Henderson
2023-04-11  1:04 ` [PATCH v2 19/54] tcg: Clear TCGLabelQemuLdst on allocation Richard Henderson
2023-04-21 22:20   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:45   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` Richard Henderson [this message]
2023-04-21 22:19   ` [PATCH v2 21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:43   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 23/54] tcg/mips: " Richard Henderson
2023-04-11  1:04 ` [PATCH v2 24/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-11  1:04 ` [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 19:06   ` Daniel Henrique Barboza
2023-04-23 18:48   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 26/54] tcg/s390x: Pass TCGType " Richard Henderson
2023-04-21 22:15   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2023-04-12 20:18   ` Daniel Henrique Barboza
2023-04-13  7:12     ` Richard Henderson
2023-04-13  9:55       ` Daniel Henrique Barboza
2023-04-13  9:55   ` Daniel Henrique Barboza
2023-04-23 18:33   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 20:19   ` Daniel Henrique Barboza
2023-04-23 18:35   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 29/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-04-21 22:27   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 30/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-21 22:28   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 31/54] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-04-21 22:29   ` Philippe Mathieu-Daudé
2023-04-23  7:30     ` Richard Henderson
2023-04-11  1:04 ` [PATCH v2 32/54] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-04-23 18:50   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 33/54] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-04-23 18:55   ` Philippe Mathieu-Daudé
2023-04-24  4:36     ` Richard Henderson
2023-04-11  1:04 ` [PATCH v2 34/54] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-04-23 18:57   ` Philippe Mathieu-Daudé
2023-04-11  1:04 ` [PATCH v2 35/54] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-04-11  1:04 ` [PATCH v2 36/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-04-11  1:04 ` [PATCH v2 37/54] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-04-11  1:04 ` [PATCH v2 38/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11  1:04 ` [PATCH v2 39/54] tcg/arm: " Richard Henderson
2023-04-11  1:04 ` [PATCH v2 40/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path Richard Henderson
2023-04-11  1:04 ` [PATCH v2 41/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11  1:05 ` [PATCH v2 42/54] tcg/ppc: " Richard Henderson
2023-04-12 19:06   ` Daniel Henrique Barboza
2023-04-11  1:05 ` [PATCH v2 43/54] tcg/riscv: " Richard Henderson
2023-04-12 20:19   ` Daniel Henrique Barboza
2023-04-11  1:05 ` [PATCH v2 44/54] tcg/s390x: " Richard Henderson
2023-04-11  1:05 ` [PATCH v2 45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11  1:05 ` [PATCH v2 46/54] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-04-11  1:05 ` [PATCH v2 47/54] tcg/mips: Reorg tcg_out_tlb_load Richard Henderson
2023-04-11  1:05 ` [PATCH v2 48/54] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11  1:05 ` [PATCH v2 49/54] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-04-12 19:09   ` Daniel Henrique Barboza
2023-04-11  1:05 ` [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-04-12 19:09   ` Daniel Henrique Barboza
2023-04-11  1:05 ` [PATCH v2 51/54] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-04-12 19:09   ` Daniel Henrique Barboza
2023-04-11  1:05 ` [PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-12 20:20   ` Daniel Henrique Barboza
2023-04-11  1:05 ` [PATCH v2 53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Richard Henderson
2023-04-11  1:05 ` [PATCH v2 54/54] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230411010512.5375-22-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=qemu-s390x@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).