From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
qemu-riscv@nongnu.org, qemu-ppc@nongnu.org
Subject: [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
Date: Mon, 10 Apr 2023 18:04:43 -0700 [thread overview]
Message-ID: <20230411010512.5375-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org>
Interpret the variable argument placement in the caller.
Mark the argument register const, because they must be passed to
add_qemu_ldst_label unmodified. This requires a bit of local
variable renaming, because addrlo was being modified.
Pass data_type instead of is64 -- there are several places where
we already convert back from bool to type. Clean things up by
using type throughout.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 164 +++++++++++++++++++++------------------
1 file changed, 89 insertions(+), 75 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 77abb7d20c..90093a6509 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2118,7 +2118,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
+ TCGType type, MemOpIdx oi,
TCGReg datalo_reg, TCGReg datahi_reg,
TCGReg addrlo_reg, TCGReg addrhi_reg,
tcg_insn_unit *raddr, tcg_insn_unit *lptr)
@@ -2126,6 +2127,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGLabelQemuLdst *label = new_ldst_label(s);
label->is_ld = is_ld;
+ label->type = type;
label->oi = oi;
label->datalo_reg = datalo_reg;
label->datahi_reg = datahi_reg;
@@ -2288,30 +2290,19 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
#endif /* SOFTMMU */
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
+static void tcg_out_qemu_ld(TCGContext *s,
+ const TCGReg datalo, const TCGReg datahi,
+ const TCGReg addrlo, const TCGReg addrhi,
+ const MemOpIdx oi, TCGType data_type)
{
- TCGReg datalo, datahi, addrlo, rbase;
- TCGReg addrhi __attribute__((unused));
- MemOpIdx oi;
- MemOp opc, s_bits;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
+ TCGReg rbase, index;
+
#ifdef CONFIG_SOFTMMU
- int mem_index;
tcg_insn_unit *label_ptr;
-#else
- unsigned a_bits;
-#endif
- datalo = *args++;
- datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
- s_bits = opc & MO_SIZE;
-
-#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
+ index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
/* Load a pointer into the current opcode w/conditional branch-link. */
label_ptr = s->code_ptr;
@@ -2319,80 +2310,71 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
rbase = TCG_REG_R3;
#else /* !CONFIG_SOFTMMU */
- a_bits = get_alignment_bits(opc);
+ unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
}
rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
- addrlo = TCG_REG_TMP1;
+ index = TCG_REG_TMP1;
+ } else {
+ index = addrlo;
}
#endif
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, rbase, index));
tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
} else if (rbase != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4));
+ tcg_out32(s, LWZX | TAB(datahi, rbase, index));
tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
- } else if (addrlo == datahi) {
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
+ } else if (index == datahi) {
+ tcg_out32(s, LWZ | TAI(datalo, index, 4));
+ tcg_out32(s, LWZ | TAI(datahi, index, 0));
} else {
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
+ tcg_out32(s, LWZ | TAI(datahi, index, 0));
+ tcg_out32(s, LWZ | TAI(datalo, index, 4));
}
} else {
uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
if (!have_isa_2_06 && insn == LDBRX) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, rbase, index));
tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
} else if (insn) {
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, insn | TAB(datalo, rbase, index));
} else {
insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, insn | TAB(datalo, rbase, index));
tcg_out_movext(s, TCG_TYPE_REG, datalo,
TCG_TYPE_REG, opc & MO_SSIZE, datalo);
}
}
#ifdef CONFIG_SOFTMMU
- add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
+ add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
+ addrlo, addrhi, s->code_ptr, label_ptr);
#endif
}
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
+static void tcg_out_qemu_st(TCGContext *s,
+ const TCGReg datalo, const TCGReg datahi,
+ const TCGReg addrlo, const TCGReg addrhi,
+ const MemOpIdx oi, TCGType data_type)
{
- TCGReg datalo, datahi, addrlo, rbase;
- TCGReg addrhi __attribute__((unused));
- MemOpIdx oi;
- MemOp opc, s_bits;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
+ TCGReg rbase, index;
+
#ifdef CONFIG_SOFTMMU
- int mem_index;
tcg_insn_unit *label_ptr;
-#else
- unsigned a_bits;
-#endif
- datalo = *args++;
- datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
- s_bits = opc & MO_SIZE;
-
-#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
+ index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
/* Load a pointer into the current opcode w/conditional branch-link. */
label_ptr = s->code_ptr;
@@ -2400,45 +2382,47 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
rbase = TCG_REG_R3;
#else /* !CONFIG_SOFTMMU */
- a_bits = get_alignment_bits(opc);
+ unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
}
rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
- addrlo = TCG_REG_TMP1;
+ index = TCG_REG_TMP1;
+ } else {
+ index = addrlo;
}
#endif
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4));
+ tcg_out32(s, STWBRX | SAB(datalo, rbase, index));
tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
} else if (rbase != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4));
+ tcg_out32(s, STWX | SAB(datahi, rbase, index));
tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
} else {
- tcg_out32(s, STW | TAI(datahi, addrlo, 0));
- tcg_out32(s, STW | TAI(datalo, addrlo, 4));
+ tcg_out32(s, STW | TAI(datahi, index, 0));
+ tcg_out32(s, STW | TAI(datalo, index, 4));
}
} else {
uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
if (!have_isa_2_06 && insn == STDBRX) {
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
+ tcg_out32(s, STWBRX | SAB(datalo, rbase, index));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, index, 4));
tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
} else {
- tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
+ tcg_out32(s, insn | SAB(datalo, rbase, index));
}
}
#ifdef CONFIG_SOFTMMU
- add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
+ add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
+ addrlo, addrhi, s->code_ptr, label_ptr);
#endif
}
@@ -2972,16 +2956,46 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, false);
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
+ tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
+ args[2], TCG_TYPE_I32);
+ } else {
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
+ args[3], TCG_TYPE_I32);
+ }
break;
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, true);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
+ args[2], TCG_TYPE_I64);
+ } else if (TARGET_LONG_BITS == 32) {
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
+ args[3], TCG_TYPE_I64);
+ } else {
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
+ args[4], TCG_TYPE_I64);
+ }
break;
case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, false);
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
+ tcg_out_qemu_st(s, args[0], -1, args[1], -1,
+ args[2], TCG_TYPE_I32);
+ } else {
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
+ args[3], TCG_TYPE_I32);
+ }
break;
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, true);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_qemu_st(s, args[0], -1, args[1], -1,
+ args[2], TCG_TYPE_I64);
+ } else if (TARGET_LONG_BITS == 32) {
+ tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
+ args[3], TCG_TYPE_I64);
+ } else {
+ tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
+ args[4], TCG_TYPE_I64);
+ }
break;
case INDEX_op_setcond_i32:
--
2.34.1
next prev parent reply other threads:[~2023-04-11 1:11 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 1:04 [PATCH v2 00/54] tcg: Simplify calls to load/store helpers Richard Henderson
2023-04-11 1:04 ` [PATCH v2 01/54] tcg: Replace if + tcg_abort with tcg_debug_assert Richard Henderson
2023-04-21 22:11 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 02/54] tcg: Replace tcg_abort with g_assert_not_reached Richard Henderson
2023-04-21 22:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 03/54] tcg: Split out tcg_out_ext8s Richard Henderson
2023-04-21 22:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 04/54] tcg: Split out tcg_out_ext8u Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 05/54] tcg: Split out tcg_out_ext16s Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 06/54] tcg: Split out tcg_out_ext16u Richard Henderson
2023-04-21 22:09 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 07/54] tcg: Split out tcg_out_ext32s Richard Henderson
2023-04-21 22:38 ` Philippe Mathieu-Daudé
2023-04-21 22:42 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 08/54] tcg: Split out tcg_out_ext32u Richard Henderson
2023-04-21 22:40 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 09/54] tcg: Split out tcg_out_exts_i32_i64 Richard Henderson
2023-04-21 22:44 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 10/54] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 11/54] tcg/mips: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 12/54] tcg/riscv: " Richard Henderson
2023-04-12 20:01 ` Daniel Henrique Barboza
2023-04-11 1:04 ` [PATCH v2 13/54] tcg: Split out tcg_out_extu_i32_i64 Richard Henderson
2023-04-21 22:46 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 14/54] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 15/54] tcg: Split out tcg_out_extrl_i64_i32 Richard Henderson
2023-04-21 22:48 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 16/54] tcg: Introduce tcg_out_movext Richard Henderson
2023-04-21 23:02 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 17/54] tcg: Introduce tcg_out_xchg Richard Henderson
2023-04-21 23:05 ` Philippe Mathieu-Daudé
2023-04-21 23:08 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 18/54] tcg: Introduce tcg_out_movext2 Richard Henderson
2023-04-11 1:04 ` [PATCH v2 19/54] tcg: Clear TCGLabelQemuLdst on allocation Richard Henderson
2023-04-21 22:20 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:45 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-21 22:19 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-23 18:43 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 23/54] tcg/mips: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 24/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-04-11 1:04 ` Richard Henderson [this message]
2023-04-12 19:06 ` [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Daniel Henrique Barboza
2023-04-23 18:48 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 26/54] tcg/s390x: Pass TCGType " Richard Henderson
2023-04-21 22:15 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2023-04-12 20:18 ` Daniel Henrique Barboza
2023-04-13 7:12 ` Richard Henderson
2023-04-13 9:55 ` Daniel Henrique Barboza
2023-04-13 9:55 ` Daniel Henrique Barboza
2023-04-23 18:33 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-12 20:19 ` Daniel Henrique Barboza
2023-04-23 18:35 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 29/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-04-21 22:27 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 30/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-04-21 22:28 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 31/54] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-04-21 22:29 ` Philippe Mathieu-Daudé
2023-04-23 7:30 ` Richard Henderson
2023-04-11 1:04 ` [PATCH v2 32/54] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-04-23 18:50 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 33/54] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-04-23 18:55 ` Philippe Mathieu-Daudé
2023-04-24 4:36 ` Richard Henderson
2023-04-11 1:04 ` [PATCH v2 34/54] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-04-23 18:57 ` Philippe Mathieu-Daudé
2023-04-11 1:04 ` [PATCH v2 35/54] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-04-11 1:04 ` [PATCH v2 36/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 37/54] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 38/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 39/54] tcg/arm: " Richard Henderson
2023-04-11 1:04 ` [PATCH v2 40/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path Richard Henderson
2023-04-11 1:04 ` [PATCH v2 41/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-04-11 1:05 ` [PATCH v2 42/54] tcg/ppc: " Richard Henderson
2023-04-12 19:06 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 43/54] tcg/riscv: " Richard Henderson
2023-04-12 20:19 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 44/54] tcg/s390x: " Richard Henderson
2023-04-11 1:05 ` [PATCH v2 45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 46/54] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-04-11 1:05 ` [PATCH v2 47/54] tcg/mips: Reorg tcg_out_tlb_load Richard Henderson
2023-04-11 1:05 ` [PATCH v2 48/54] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 49/54] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 51/54] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-04-12 19:09 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-04-12 20:20 ` Daniel Henrique Barboza
2023-04-11 1:05 ` [PATCH v2 53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Richard Henderson
2023-04-11 1:05 ` [PATCH v2 54/54] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230411010512.5375-26-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).