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From: "Michael S. Tsirkin" <mst@redhat.com>
To: Stefan Weil <sw@weilnetz.de>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	qemu-devel@nongnu.org, qemu-trivial@nongnu.org,
	Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH for-8.0] docs/cxl: Fix sentence
Date: Tue, 11 Apr 2023 03:08:40 -0400	[thread overview]
Message-ID: <20230411030721-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20230409201828.1159568-1-sw@weilnetz.de>

On Sun, Apr 09, 2023 at 10:18:28PM +0200, Stefan Weil wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> ---
> 
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
> 
> Regards,
> Stefan W.

It does but I don't think we should bother for 8.0. Nothing
bad will happen if we defer this, we need to focus on
kicking the release out of the door.

>  docs/system/devices/cxl.rst | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>  
>  CXL Root Ports (CXL RP)
>  ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
>  There are a number of CXL specific Designated Vendor Specific
>  Extended Capabilities (DVSEC) in PCIe Configuration Space
>  and associated component register access via PCI bars.
> -- 
> 2.39.2



  parent reply	other threads:[~2023-04-11  7:09 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-09 20:18 [PATCH for-8.0] docs/cxl: Fix sentence Stefan Weil via
2023-04-11  1:10 ` Richard Henderson
2023-04-11  7:08 ` Michael S. Tsirkin [this message]
2023-04-11 11:43 ` Jonathan Cameron via

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