[RFC 1/5] target/riscv: Add properties for BF16 extensions

[Weiwei Li <liweiwei@iscas.ac.cn>]

Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 13 +++++++++++++
 target/riscv/cpu.h |  3 +++
 2 files changed, 16 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..c19bbb41fb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -874,6 +874,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if ((cpu->cfg.ext_zfbfmin | cpu->cfg.ext_zvfbfmin |
+         cpu->cfg.ext_zvfbfwma) && !cpu->cfg.ext_f) {
+        error_setg(errp, "BF16 extensions require F extension");
+        return;
+    }
+
     if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
         error_setg(errp, "D extension requires F extension");
         return;
@@ -918,6 +924,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if ((cpu->cfg.ext_zvfbfmin | cpu->cfg.ext_zvfbfwma) &&
+        !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfbfmin/Zvfbfwma extensions require Zve32f "
+                         "extension");
+        return;
+    }
+
     /* Set the ISA extensions, checks should have happened above */
     if (cpu->cfg.ext_zhinx) {
         cpu->cfg.ext_zhinxmin = true;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..6c99a82624 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,6 +462,7 @@ struct RISCVCPUConfig {
     bool ext_svpbmt;
     bool ext_zdinx;
     bool ext_zawrs;
+    bool ext_zfbfmin;
     bool ext_zfh;
     bool ext_zfhmin;
     bool ext_zfinx;
@@ -471,6 +472,8 @@ struct RISCVCPUConfig {
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zmmul;
+    bool ext_zvfbfmin;
+    bool ext_zvfbfwma;
     bool ext_zvfh;
     bool ext_zvfhmin;
     bool ext_smaia;
-- 
2.25.1