From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, qemu-riscv@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v7 14/25] target/riscv: Introduce mmuidx_2stage
Date: Wed, 12 Apr 2023 13:43:22 +0200 [thread overview]
Message-ID: <20230412114333.118895-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org>
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org>
---
target/riscv/cpu.h | 1 -
target/riscv/internals.h | 5 +++++
target/riscv/cpu_helper.c | 20 ++++++--------------
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 35cf2e2691..d1f888a790 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -581,7 +581,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 4aa1cb409f..b5f823c7ec 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -51,6 +51,11 @@ static inline bool mmuidx_sum(int mmu_idx)
return (mmu_idx & 3) == MMUIdx_S_SUM;
}
+static inline bool mmuidx_2stage(int mmu_idx)
+{
+ return mmu_idx & MMU_2STAGE_BIT;
+}
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57bb19c76e..9dfd1d739b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -591,11 +591,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
}
}
-bool riscv_cpu_two_stage_lookup(int mmu_idx)
-{
- return mmu_idx & MMU_2STAGE_BIT;
-}
-
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
{
CPURISCVState *env = &cpu->env;
@@ -779,7 +774,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
}
@@ -1175,8 +1170,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1201,8 +1195,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1256,7 +1249,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
@@ -1268,7 +1261,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
pmu_tlb_fill_incr_ctr(cpu, access_type);
if (env->virt_enabled ||
- ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
+ ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
@@ -1366,8 +1359,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else {
raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error,
- env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx),
+ env->virt_enabled || mmuidx_2stage(mmu_idx),
two_stage_indirect_error);
cpu_loop_exit_restore(cs, retaddr);
}
--
2.34.1
next prev parent reply other threads:[~2023-04-12 11:44 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-12 11:43 [PATCH v7 00/25] target/riscv: MSTATUS_SUM + cleanups Richard Henderson
2023-04-12 11:43 ` [PATCH v7 01/25] target/riscv: Extract virt enabled state from tb flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 02/25] target/riscv: Add a general status enum for extensions Richard Henderson
2023-04-12 11:43 ` [PATCH v7 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 05/25] target/riscv: Add a tb flags field for vstart Richard Henderson
2023-04-12 11:43 ` [PATCH v7 06/25] target/riscv: Separate priv from mmu_idx Richard Henderson
2023-04-12 11:43 ` [PATCH v7 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change Richard Henderson
2023-04-12 11:43 ` [PATCH v7 08/25] accel/tcg: Add cpu_ld*_code_mmu Richard Henderson
2023-04-12 11:43 ` [PATCH v7 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX Richard Henderson
2023-04-12 11:43 ` [PATCH v7 10/25] target/riscv: Handle HLV, HSV via helpers Richard Henderson
2023-04-12 11:43 ` [PATCH v7 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Richard Henderson
2023-04-12 11:43 ` [PATCH v7 12/25] target/riscv: Introduce mmuidx_sum Richard Henderson
2023-04-12 11:43 ` [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv Richard Henderson
2023-04-12 11:43 ` Richard Henderson [this message]
2023-04-12 11:43 ` [PATCH v7 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv Richard Henderson
2023-04-12 11:43 ` [PATCH v7 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Richard Henderson
2023-04-12 11:43 ` [PATCH v7 17/25] target/riscv: Check SUM in the correct register Richard Henderson
2023-04-12 11:43 ` [PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers Richard Henderson
2023-04-12 11:43 ` [PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loop Richard Henderson
2023-04-12 11:43 ` [PATCH v7 20/25] target/riscv: Move leaf pte processing out of " Richard Henderson
2023-04-12 11:43 ` [PATCH v7 21/25] target/riscv: Suppress pte update with is_debug Richard Henderson
2023-04-12 11:43 ` [PATCH v7 22/25] target/riscv: Don't modify SUM " Richard Henderson
2023-04-12 11:43 ` [PATCH v7 23/25] target/riscv: Merge checks for reserved pte flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 24/25] target/riscv: Reorg access check in get_physical_address Richard Henderson
2023-04-12 11:43 ` [PATCH v7 25/25] target/riscv: Reorg sum " Richard Henderson
2023-04-17 2:11 ` [PATCH v7 00/25] target/riscv: MSTATUS_SUM + cleanups Alistair Francis
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