From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, qemu-riscv@nongnu.org,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v7 01/25] target/riscv: Extract virt enabled state from tb flags
Date: Wed, 12 Apr 2023 13:43:09 +0200 [thread overview]
Message-ID: <20230412114333.118895-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org>
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Virt enabled state is not a constant, so we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 1 +
target/riscv/translate.c | 10 +---------
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86e08d10da..aa53d0e256 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -648,6 +648,8 @@ FIELD(TB_FLAGS, VTA, 24, 1)
FIELD(TB_FLAGS, VMA, 25, 1)
/* Native debug itrigger */
FIELD(TB_FLAGS, ITRIGGER, 26, 1)
+/* Virtual mode enabled */
+FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 433ea529b0..1d90977d46 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -104,6 +104,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
get_field(env->mstatus_hs, MSTATUS_VS));
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled);
}
if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0094922b6..ebd00529ff 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1171,15 +1171,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
ctx->priv_ver = env->priv_ver;
-#if !defined(CONFIG_USER_ONLY)
- if (riscv_has_ext(env, RVH)) {
- ctx->virt_enabled = env->virt_enabled;
- } else {
- ctx->virt_enabled = false;
- }
-#else
- ctx->virt_enabled = false;
-#endif
+ ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->cfg_ptr = &(cpu->cfg);
--
2.34.1
next prev parent reply other threads:[~2023-04-12 11:44 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-12 11:43 [PATCH v7 00/25] target/riscv: MSTATUS_SUM + cleanups Richard Henderson
2023-04-12 11:43 ` Richard Henderson [this message]
2023-04-12 11:43 ` [PATCH v7 02/25] target/riscv: Add a general status enum for extensions Richard Henderson
2023-04-12 11:43 ` [PATCH v7 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 05/25] target/riscv: Add a tb flags field for vstart Richard Henderson
2023-04-12 11:43 ` [PATCH v7 06/25] target/riscv: Separate priv from mmu_idx Richard Henderson
2023-04-12 11:43 ` [PATCH v7 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change Richard Henderson
2023-04-12 11:43 ` [PATCH v7 08/25] accel/tcg: Add cpu_ld*_code_mmu Richard Henderson
2023-04-12 11:43 ` [PATCH v7 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX Richard Henderson
2023-04-12 11:43 ` [PATCH v7 10/25] target/riscv: Handle HLV, HSV via helpers Richard Henderson
2023-04-12 11:43 ` [PATCH v7 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Richard Henderson
2023-04-12 11:43 ` [PATCH v7 12/25] target/riscv: Introduce mmuidx_sum Richard Henderson
2023-04-12 11:43 ` [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv Richard Henderson
2023-04-12 11:43 ` [PATCH v7 14/25] target/riscv: Introduce mmuidx_2stage Richard Henderson
2023-04-12 11:43 ` [PATCH v7 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv Richard Henderson
2023-04-12 11:43 ` [PATCH v7 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Richard Henderson
2023-04-12 11:43 ` [PATCH v7 17/25] target/riscv: Check SUM in the correct register Richard Henderson
2023-04-12 11:43 ` [PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers Richard Henderson
2023-04-12 11:43 ` [PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loop Richard Henderson
2023-04-12 11:43 ` [PATCH v7 20/25] target/riscv: Move leaf pte processing out of " Richard Henderson
2023-04-12 11:43 ` [PATCH v7 21/25] target/riscv: Suppress pte update with is_debug Richard Henderson
2023-04-12 11:43 ` [PATCH v7 22/25] target/riscv: Don't modify SUM " Richard Henderson
2023-04-12 11:43 ` [PATCH v7 23/25] target/riscv: Merge checks for reserved pte flags Richard Henderson
2023-04-12 11:43 ` [PATCH v7 24/25] target/riscv: Reorg access check in get_physical_address Richard Henderson
2023-04-12 11:43 ` [PATCH v7 25/25] target/riscv: Reorg sum " Richard Henderson
2023-04-17 2:11 ` [PATCH v7 00/25] target/riscv: MSTATUS_SUM + cleanups Alistair Francis
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