From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 5/6] target/riscv: flush tb when PMP entry changes
Date: Thu, 13 Apr 2023 17:01:21 +0800 [thread overview]
Message-ID: <20230413090122.65228-6-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230413090122.65228-1-liweiwei@iscas.ac.cn>
The translation block may also be affected when PMP entry changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index aced23c4d5..c2db52361f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -25,6 +25,7 @@
#include "cpu.h"
#include "trace.h"
#include "exec/exec-all.h"
+#include "exec/tb-flush.h"
static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
@@ -492,6 +493,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
/* If PMP permission of any addr has been changed, flush TLB pages. */
if (modified) {
tlb_flush(env_cpu(env));
+ tb_flush(env_cpu(env));
}
}
@@ -545,6 +547,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
tlb_flush(env_cpu(env));
+ tb_flush(env_cpu(env));
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
--
2.25.1
next prev parent reply other threads:[~2023-04-13 9:04 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-13 9:01 [PATCH 0/6] target/riscv: Fix PMP related problem Weiwei Li
2023-04-13 9:01 ` [PATCH 1/6] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-04-18 2:53 ` Alistair Francis
2023-04-18 3:05 ` Weiwei Li
2023-04-18 5:18 ` LIU Zhiwei
2023-04-18 6:09 ` Weiwei Li
2023-04-18 7:08 ` LIU Zhiwei
2023-04-18 8:01 ` Weiwei Li
2023-04-13 9:01 ` [PATCH 2/6] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-04-18 2:54 ` Alistair Francis
2023-04-13 9:01 ` [PATCH 3/6] target/riscv: flush tlb when pmpaddr is updated Weiwei Li
2023-04-18 2:36 ` Alistair Francis
2023-04-18 7:11 ` LIU Zhiwei
2023-04-18 8:13 ` Weiwei Li
2023-04-13 9:01 ` [PATCH 4/6] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Weiwei Li
2023-04-18 2:39 ` Alistair Francis
2023-04-18 7:14 ` LIU Zhiwei
2023-04-13 9:01 ` Weiwei Li [this message]
2023-04-18 7:28 ` [PATCH 5/6] target/riscv: flush tb when PMP entry changes LIU Zhiwei
2023-04-13 9:01 ` [PATCH 6/6] accel/tcg: Remain TLB_INVALID_MASK in the address when TLB is re-filled Weiwei Li
2023-04-17 16:25 ` Daniel Henrique Barboza
2023-04-18 0:48 ` Weiwei Li
2023-04-18 7:18 ` Richard Henderson
2023-04-18 7:36 ` Richard Henderson
2023-04-18 8:18 ` Weiwei Li
2023-04-18 3:07 ` [PATCH 0/6] target/riscv: Fix PMP related problem LIU Zhiwei
2023-04-18 3:36 ` Weiwei Li
2023-04-18 4:47 ` LIU Zhiwei
2023-04-18 6:11 ` Weiwei Li
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