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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/21] target/arm: Implement FEAT_PAN3
Date: Thu, 20 Apr 2023 11:04:49 +0100	[thread overview]
Message-ID: <20230420100456.944969-15-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org>

FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows
the PAN bit to make memory non-privileged-read/write if it is
user-executable as well as if it is user-read/write.

Implement this feature and enable it in the AArch64 'max' CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230331145045.2584941-4-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst |  1 +
 target/arm/cpu.h              |  5 +++++
 target/arm/cpu64.c            |  2 +-
 target/arm/ptw.c              | 14 +++++++++++++-
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 2062d712610..73389878755 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -56,6 +56,7 @@ the following architecture extensions:
 - FEAT_MTE3 (MTE Asymmetric Fault Handling)
 - FEAT_PAN (Privileged access never)
 - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
+- FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
 - FEAT_PAuth (Pointer authentication)
 - FEAT_PMULL (PMULL, PMULL2 instructions)
 - FEAT_PMUv3p1 (PMU Extensions v3.1)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c097cae9882..d469a2637b3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3823,6 +3823,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
 }
 
+static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
+}
+
 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0fb07cc7b6d..735ca541634 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1302,7 +1302,7 @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
     t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
     t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
     t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6d72950a795..bd75da8dbcf 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -947,6 +947,7 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
                       int ap, int ns, int xn, int pxn)
 {
+    ARMCPU *cpu = env_archcpu(env);
     bool is_user = regime_is_user(env, mmu_idx);
     int prot_rw, user_rw;
     bool have_wxn;
@@ -958,8 +959,19 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
     if (is_user) {
         prot_rw = user_rw;
     } else {
+        /*
+         * PAN controls can forbid data accesses but don't affect insn fetch.
+         * Plain PAN forbids data accesses if EL0 has data permissions;
+         * PAN3 forbids data accesses if EL0 has either data or exec perms.
+         * Note that for AArch64 the 'user can exec' case is exactly !xn.
+         * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0
+         * do not affect EPAN.
+         */
         if (user_rw && regime_is_pan(env, mmu_idx)) {
-            /* PAN forbids data accesses but doesn't affect insn fetch */
+            prot_rw = 0;
+        } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 &&
+                   regime_is_pan(env, mmu_idx) &&
+                   (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) {
             prot_rw = 0;
         } else {
             prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
-- 
2.34.1



  parent reply	other threads:[~2023-04-20 10:06 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-20 10:04 [PULL 00/21] target-arm queue Peter Maydell
2023-04-20 10:04 ` [PULL 01/21] hw/arm: Fix some typos in comments (most found by codespell) Peter Maydell
2023-04-20 10:04 ` [PULL 02/21] exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf Peter Maydell
2023-04-20 10:04 ` [PULL 03/21] hw/watchdog: Allwinner WDT emulation for system reset Peter Maydell
2023-04-20 10:04 ` [PULL 04/21] hw/arm: Add WDT to Allwinner-A10 and Cubieboard Peter Maydell
2023-04-20 10:04 ` [PULL 05/21] hw/arm: Add WDT to Allwinner-H3 and Orangepi-PC Peter Maydell
2023-04-20 10:04 ` [PULL 06/21] tests/avocado: Add reboot tests to Cubieboard Peter Maydell
2023-04-20 10:04 ` [PULL 07/21] hw/timer/imx_epit: don't shadow variable Peter Maydell
2023-04-20 10:04 ` [PULL 08/21] hw/timer/imx_epit: fix limit check Peter Maydell
2023-04-20 10:04 ` [PULL 09/21] target/arm: Remove KVM AArch32 CPU definitions Peter Maydell
2023-04-20 10:04 ` [PULL 10/21] hw/arm/virt: Restrict Cortex-A7 check to TCG Peter Maydell
2023-04-20 10:04 ` [PULL 11/21] target/arm: Initialize debug capabilities only once Peter Maydell
2023-04-20 10:04 ` [PULL 12/21] target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort() Peter Maydell
2023-04-20 10:04 ` [PULL 13/21] target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2 Peter Maydell
2023-04-20 10:04 ` Peter Maydell [this message]
2023-04-20 10:04 ` [PULL 15/21] docs/devel/kconfig.rst: Fix incorrect markup Peter Maydell
2023-04-20 10:04 ` [PULL 16/21] target/arm: Report pauth information to gdb as 'pauth_v2' Peter Maydell
2023-04-20 10:04 ` [PULL 17/21] hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO bus Peter Maydell
2023-04-20 10:04 ` [PULL 18/21] fsl-imx6ul: Add fec[12]-phy-connected properties Peter Maydell
2023-04-20 10:04 ` [PULL 19/21] arm/mcimx6ul-evk: Set fec1-phy-connected property to false Peter Maydell
2023-04-20 10:04 ` [PULL 20/21] fsl-imx7: Add fec[12]-phy-connected properties Peter Maydell
2023-04-20 10:04 ` [PULL 21/21] arm/mcimx7d-sabre: Set fec2-phy-connected property to false Peter Maydell
2023-04-21 10:49 ` [PULL 00/21] target-arm queue Richard Henderson
2023-04-21 11:54   ` Peter Maydell

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