* [PULL 1/7] docs: Add support for TPM devices over I2C bus
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-20 12:32 ` [PULL 2/7] tpm: Extend common APIs to support TPM TIS I2C Stefan Berger
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Ninad Palsule, Stefan Berger,
Cédric Le Goater, Joel Stanley
From: Ninad Palsule <ninad@linux.ibm.com>
This is a documentation change for I2C TPM device support.
Qemu already supports devices attached to ISA and sysbus.
This drop adds support for the I2C bus attached TPM devices.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20230414220754.1191476-2-ninadpalsule@us.ibm.com
---
docs/specs/tpm.rst | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
index 535912a92b..efe124a148 100644
--- a/docs/specs/tpm.rst
+++ b/docs/specs/tpm.rst
@@ -21,12 +21,16 @@ QEMU files related to TPM TIS interface:
- ``hw/tpm/tpm_tis_common.c``
- ``hw/tpm/tpm_tis_isa.c``
- ``hw/tpm/tpm_tis_sysbus.c``
+ - ``hw/tpm/tpm_tis_i2c.c``
- ``hw/tpm/tpm_tis.h``
Both an ISA device and a sysbus device are available. The former is
used with pc/q35 machine while the latter can be instantiated in the
Arm virt machine.
+An I2C device support is also provided which can be instantiated in the Arm
+based emulation machines. This device only supports the TPM 2 protocol.
+
CRB interface
-------------
@@ -348,6 +352,23 @@ In case an Arm virt machine is emulated, use the following command line:
-drive if=pflash,format=raw,file=flash0.img,readonly=on \
-drive if=pflash,format=raw,file=flash1.img
+In case a ast2600-evb bmc machine is emulated and you want to use a TPM device
+attached to I2C bus, use the following command line:
+
+.. code-block:: console
+
+ qemu-system-arm -M ast2600-evb -nographic \
+ -kernel arch/arm/boot/zImage \
+ -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
+ -initrd rootfs.cpio \
+ -chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \
+ -tpmdev emulator,id=tpm0,chardev=chrtpm \
+ -device tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e
+
+ For testing, use this command to load the driver to the correct address
+
+ echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device
+
In case SeaBIOS is used as firmware, it should show the TPM menu item
after entering the menu with 'ESC'.
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 2/7] tpm: Extend common APIs to support TPM TIS I2C
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
2023-04-20 12:32 ` [PULL 1/7] docs: Add support for TPM devices over I2C bus Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-20 12:32 ` [PULL 3/7] tpm: Add support for TPM device over I2C bus Stefan Berger
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Ninad Palsule, Stefan Berger,
Cédric Le Goater, Joel Stanley
From: Ninad Palsule <ninad@linux.ibm.com>
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices.
This commit includes changes for the common code.
- Added support for the new checksum registers which are required for
the I2C support. The checksum calculation is handled in the qemu
common code.
- Added wrapper function for read and write data so that I2C code can
call it without MMIO interface.
The TPM TIS I2C spec describes in the table in section "Interface Locality
Usage per Register" that the TPM_INT_ENABLE and TPM_INT_STATUS registers
must be writable for any locality even if the locality is not the active
locality. Therefore, remove the checks whether the writing locality is the
active locality for these registers.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Message-id: 20230414220754.1191476-3-ninadpalsule@us.ibm.com
---
hw/tpm/tpm_tis.h | 3 +++
hw/tpm/tpm_tis_common.c | 36 ++++++++++++++++++++++++++++--------
include/hw/acpi/tpm.h | 41 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 72 insertions(+), 8 deletions(-)
diff --git a/hw/tpm/tpm_tis.h b/hw/tpm/tpm_tis.h
index f6b5872ba6..6f29a508dd 100644
--- a/hw/tpm/tpm_tis.h
+++ b/hw/tpm/tpm_tis.h
@@ -86,5 +86,8 @@ int tpm_tis_pre_save(TPMState *s);
void tpm_tis_reset(TPMState *s);
enum TPMVersion tpm_tis_get_tpm_version(TPMState *s);
void tpm_tis_request_completed(TPMState *s, int ret);
+uint32_t tpm_tis_read_data(TPMState *s, hwaddr addr, unsigned size);
+void tpm_tis_write_data(TPMState *s, hwaddr addr, uint64_t val, uint32_t size);
+uint16_t tpm_tis_get_checksum(TPMState *s);
#endif /* TPM_TPM_TIS_H */
diff --git a/hw/tpm/tpm_tis_common.c b/hw/tpm/tpm_tis_common.c
index 503be2a541..c07c179dbc 100644
--- a/hw/tpm/tpm_tis_common.c
+++ b/hw/tpm/tpm_tis_common.c
@@ -26,6 +26,8 @@
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "qapi/error.h"
+#include "qemu/bswap.h"
+#include "qemu/crc-ccitt.h"
#include "qemu/module.h"
#include "hw/acpi/tpm.h"
@@ -447,6 +449,23 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
return val;
}
+/*
+ * A wrapper read function so that it can be directly called without
+ * mmio.
+ */
+uint32_t tpm_tis_read_data(TPMState *s, hwaddr addr, unsigned size)
+{
+ return tpm_tis_mmio_read(s, addr, size);
+}
+
+/*
+ * Calculate current data buffer checksum
+ */
+uint16_t tpm_tis_get_checksum(TPMState *s)
+{
+ return bswap16(crc_ccitt(0, s->buffer, s->rw_offset));
+}
+
/*
* Write a value to a register of the TIS interface
* See specs pages 33-63 for description of the registers
@@ -588,10 +607,6 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
break;
case TPM_TIS_REG_INT_ENABLE:
- if (s->active_locty != locty) {
- break;
- }
-
s->loc[locty].inte &= mask;
s->loc[locty].inte |= (val & (TPM_TIS_INT_ENABLED |
TPM_TIS_INT_POLARITY_MASK |
@@ -601,10 +616,6 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
/* hard wired -- ignore */
break;
case TPM_TIS_REG_INT_STATUS:
- if (s->active_locty != locty) {
- break;
- }
-
/* clearing of interrupt flags */
if (((val & TPM_TIS_INTERRUPTS_SUPPORTED)) &&
(s->loc[locty].ints & TPM_TIS_INTERRUPTS_SUPPORTED)) {
@@ -767,6 +778,15 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
}
}
+/*
+ * A wrapper write function so that it can be directly called without
+ * mmio.
+ */
+void tpm_tis_write_data(TPMState *s, hwaddr addr, uint64_t val, uint32_t size)
+{
+ tpm_tis_mmio_write(s, addr, val, size);
+}
+
const MemoryRegionOps tpm_tis_memory_ops = {
.read = tpm_tis_mmio_read,
.write = tpm_tis_mmio_write,
diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h
index 559ba6906c..579c45f5ba 100644
--- a/include/hw/acpi/tpm.h
+++ b/include/hw/acpi/tpm.h
@@ -93,6 +93,7 @@
#define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9)
#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8)
+#define TPM_TIS_CAP_BURST_COUNT_STATIC (1 << 8)
#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */
#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \
(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
@@ -209,6 +210,46 @@ REG32(CRB_DATA_BUFFER, 0x80)
#define TPM_PPI_FUNC_ALLOWED_USR_NOT_REQ (4 << 0)
#define TPM_PPI_FUNC_MASK (7 << 0)
+/* TPM TIS I2C registers */
+#define TPM_I2C_REG_LOC_SEL 0x00
+#define TPM_I2C_REG_ACCESS 0x04
+#define TPM_I2C_REG_INT_ENABLE 0x08
+#define TPM_I2C_REG_INT_CAPABILITY 0x14
+#define TPM_I2C_REG_STS 0x18
+#define TPM_I2C_REG_DATA_FIFO 0x24
+#define TPM_I2C_REG_INTF_CAPABILITY 0x30
+#define TPM_I2C_REG_I2C_DEV_ADDRESS 0x38
+#define TPM_I2C_REG_DATA_CSUM_ENABLE 0x40
+#define TPM_I2C_REG_DATA_CSUM_GET 0x44
+#define TPM_I2C_REG_DID_VID 0x48
+#define TPM_I2C_REG_RID 0x4c
+#define TPM_I2C_REG_UNKNOWN 0xff
+
+/* I2C specific interface capabilities */
+#define TPM_I2C_CAP_INTERFACE_TYPE (0x2 << 0) /* FIFO interface */
+#define TPM_I2C_CAP_INTERFACE_VER (0x0 << 4) /* TCG I2C intf 1.0 */
+#define TPM_I2C_CAP_TPM2_FAMILY (0x1 << 7) /* TPM 2.0 family. */
+#define TPM_I2C_CAP_DEV_ADDR_CHANGE (0x0 << 27) /* No dev addr chng */
+#define TPM_I2C_CAP_BURST_COUNT_STATIC (0x1 << 29) /* Burst count static */
+#define TPM_I2C_CAP_LOCALITY_CAP (0x1 << 25) /* 0-5 locality */
+#define TPM_I2C_CAP_BUS_SPEED (3 << 21) /* std and fast mode */
+
+/*
+ * TPM_I2C_STS masks for read/writing bits from/to TIS
+ * TPM_STS mask for read bits 31:26 must be zero
+ */
+#define TPM_I2C_STS_READ_MASK 0x00ffffdd
+#define TPM_I2C_STS_WRITE_MASK 0x03000062
+
+/* Checksum enabled. */
+#define TPM_DATA_CSUM_ENABLED 0x1
+
+/*
+ * TPM_I2C_INT_ENABLE mask. Linux kernel does not support
+ * interrupts hence setting it to 0.
+ */
+#define TPM_I2C_INT_ENABLE_MASK 0x0
+
void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);
#endif /* CONFIG_TPM */
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 3/7] tpm: Add support for TPM device over I2C bus
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
2023-04-20 12:32 ` [PULL 1/7] docs: Add support for TPM devices over I2C bus Stefan Berger
2023-04-20 12:32 ` [PULL 2/7] tpm: Extend common APIs to support TPM TIS I2C Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-20 12:32 ` [PULL 4/7] tests/avocado/aspeed: Add TPM TIS I2C test Stefan Berger
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Ninad Palsule, Stefan Berger,
Cédric Le Goater, Joel Stanley
From: Ninad Palsule <ninad@linux.ibm.com>
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices. I2C model only supports
TPM2 protocol.
This commit includes changes for the common code.
- Added I2C emulation model. Logic was added in the model to temporarily
cache the data as I2C interface works per byte basis.
- New tpm type "tpm-tis-i2c" added for I2C support. The user has to
provide this string on command line.
Testing:
TPM I2C device module is tested using SWTPM (software based TPM
package). Qemu uses the rainier machine and is connected to swtpm over
the socket interface.
The command to start swtpm is as follows:
$ swtpm socket --tpmstate dir=/tmp/mytpm1 \
--ctrl type=unixio,path=/tmp/mytpm1/swtpm-sock \
--tpm2 --log level=100
The command to start qemu is as follows:
$ qemu-system-arm -M rainier-bmc -nographic \
-kernel ${IMAGEPATH}/fitImage-linux.bin \
-dtb ${IMAGEPATH}/aspeed-bmc-ibm-rainier.dtb \
-initrd ${IMAGEPATH}/obmc-phosphor-initramfs.rootfs.cpio.xz \
-drive file=${IMAGEPATH}/obmc-phosphor-image.rootfs.wic.qcow2,if=sd,index=2 \
-net nic -net user,hostfwd=:127.0.0.1:2222-:22,hostfwd=:127.0.0.1:2443-:443 \
-chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \
-tpmdev emulator,id=tpm0,chardev=chrtpm \
-device tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Message-id: 20230414220754.1191476-4-ninadpalsule@us.ibm.com
---
hw/arm/Kconfig | 1 +
hw/tpm/Kconfig | 7 +
hw/tpm/meson.build | 1 +
hw/tpm/tpm_tis_i2c.c | 571 +++++++++++++++++++++++++++++++++++++++++++
hw/tpm/trace-events | 6 +
include/sysemu/tpm.h | 3 +
6 files changed, 589 insertions(+)
create mode 100644 hw/tpm/tpm_tis_i2c.c
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b5aed4aff5..05d6ef1a31 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -6,6 +6,7 @@ config ARM_VIRT
imply VFIO_PLATFORM
imply VFIO_XGMAC
imply TPM_TIS_SYSBUS
+ imply TPM_TIS_I2C
imply NVDIMM
select ARM_GIC
select ACPI
diff --git a/hw/tpm/Kconfig b/hw/tpm/Kconfig
index 29e82f3c92..a46663288c 100644
--- a/hw/tpm/Kconfig
+++ b/hw/tpm/Kconfig
@@ -1,3 +1,10 @@
+config TPM_TIS_I2C
+ bool
+ depends on TPM
+ select TPM_BACKEND
+ select I2C
+ select TPM_TIS
+
config TPM_TIS_ISA
bool
depends on TPM && ISA_BUS
diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build
index 7abc2d794a..76fe3cb098 100644
--- a/hw/tpm/meson.build
+++ b/hw/tpm/meson.build
@@ -1,6 +1,7 @@
softmmu_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_tis_common.c'))
softmmu_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c'))
softmmu_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbus.c'))
+softmmu_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c'))
softmmu_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c'))
softmmu_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_ppi.c'))
softmmu_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_ppi.c'))
diff --git a/hw/tpm/tpm_tis_i2c.c b/hw/tpm/tpm_tis_i2c.c
new file mode 100644
index 0000000000..b695fd3a46
--- /dev/null
+++ b/hw/tpm/tpm_tis_i2c.c
@@ -0,0 +1,571 @@
+/*
+ * tpm_tis_i2c.c - QEMU's TPM TIS I2C Device
+ *
+ * Copyright (c) 2023 IBM Corporation
+ *
+ * Authors:
+ * Ninad Palsule <ninad@linux.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * TPM I2C implementation follows TCG TPM I2c Interface specification,
+ * Family 2.0, Level 00, Revision 1.00
+ *
+ * TPM TIS for TPM 2 implementation following TCG PC Client Platform
+ * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/i2c/i2c.h"
+#include "hw/sysbus.h"
+#include "hw/acpi/tpm.h"
+#include "migration/vmstate.h"
+#include "tpm_prop.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "tpm_tis.h"
+
+/* Operations */
+#define OP_SEND 1
+#define OP_RECV 2
+
+/* Is locality valid */
+#define TPM_TIS_I2C_IS_VALID_LOCTY(x) TPM_TIS_IS_VALID_LOCTY(x)
+
+typedef struct TPMStateI2C {
+ /*< private >*/
+ I2CSlave parent_obj;
+
+ uint8_t offset; /* offset into data[] */
+ uint8_t operation; /* OP_SEND & OP_RECV */
+ uint8_t data[5]; /* Data */
+
+ /* i2c registers */
+ uint8_t loc_sel; /* Current locality */
+ uint8_t csum_enable; /* Is checksum enabled */
+
+ /* Derived from the above */
+ const char *reg_name; /* Register name */
+ uint32_t tis_addr; /* Converted tis address including locty */
+
+ /*< public >*/
+ TPMState state; /* not a QOM object */
+
+} TPMStateI2C;
+
+DECLARE_INSTANCE_CHECKER(TPMStateI2C, TPM_TIS_I2C,
+ TYPE_TPM_TIS_I2C)
+
+/* Prototype */
+static inline void tpm_tis_i2c_to_tis_reg(TPMStateI2C *i2cst, uint8_t i2c_reg);
+
+/* Register map */
+typedef struct regMap {
+ uint8_t i2c_reg; /* I2C register */
+ uint16_t tis_reg; /* TIS register */
+ const char *reg_name; /* Register name */
+} I2CRegMap;
+
+/*
+ * The register values in the common code is different than the latest
+ * register numbers as per the spec hence add the conversion map
+ */
+static const I2CRegMap tpm_tis_reg_map[] = {
+ /*
+ * These registers are sent to TIS layer. The register with UNKNOWN
+ * mapping are not sent to TIS layer and handled in I2c layer.
+ * NOTE: Adding frequently used registers at the start
+ */
+ { TPM_I2C_REG_DATA_FIFO, TPM_TIS_REG_DATA_FIFO, "FIFO", },
+ { TPM_I2C_REG_STS, TPM_TIS_REG_STS, "STS", },
+ { TPM_I2C_REG_DATA_CSUM_GET, TPM_I2C_REG_UNKNOWN, "CSUM_GET", },
+ { TPM_I2C_REG_LOC_SEL, TPM_I2C_REG_UNKNOWN, "LOC_SEL", },
+ { TPM_I2C_REG_ACCESS, TPM_TIS_REG_ACCESS, "ACCESS", },
+ { TPM_I2C_REG_INT_ENABLE, TPM_TIS_REG_INT_ENABLE, "INTR_ENABLE",},
+ { TPM_I2C_REG_INT_CAPABILITY, TPM_I2C_REG_UNKNOWN, "INTR_CAP", },
+ { TPM_I2C_REG_INTF_CAPABILITY, TPM_TIS_REG_INTF_CAPABILITY, "INTF_CAP", },
+ { TPM_I2C_REG_DID_VID, TPM_TIS_REG_DID_VID, "DID_VID", },
+ { TPM_I2C_REG_RID, TPM_TIS_REG_RID, "RID", },
+ { TPM_I2C_REG_I2C_DEV_ADDRESS, TPM_I2C_REG_UNKNOWN, "DEV_ADDRESS",},
+ { TPM_I2C_REG_DATA_CSUM_ENABLE, TPM_I2C_REG_UNKNOWN, "CSUM_ENABLE",},
+};
+
+static int tpm_tis_i2c_pre_save(void *opaque)
+{
+ TPMStateI2C *i2cst = opaque;
+
+ return tpm_tis_pre_save(&i2cst->state);
+}
+
+static int tpm_tis_i2c_post_load(void *opaque, int version_id)
+{
+ TPMStateI2C *i2cst = opaque;
+
+ if (i2cst->offset >= 1) {
+ tpm_tis_i2c_to_tis_reg(i2cst, i2cst->data[0]);
+ }
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_tpm_tis_i2c = {
+ .name = "tpm-tis-i2c",
+ .version_id = 0,
+ .pre_save = tpm_tis_i2c_pre_save,
+ .post_load = tpm_tis_i2c_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_BUFFER(state.buffer, TPMStateI2C),
+ VMSTATE_UINT16(state.rw_offset, TPMStateI2C),
+ VMSTATE_UINT8(state.active_locty, TPMStateI2C),
+ VMSTATE_UINT8(state.aborting_locty, TPMStateI2C),
+ VMSTATE_UINT8(state.next_locty, TPMStateI2C),
+
+ VMSTATE_STRUCT_ARRAY(state.loc, TPMStateI2C, TPM_TIS_NUM_LOCALITIES, 0,
+ vmstate_locty, TPMLocality),
+
+ /* i2c specifics */
+ VMSTATE_UINT8(offset, TPMStateI2C),
+ VMSTATE_UINT8(operation, TPMStateI2C),
+ VMSTATE_BUFFER(data, TPMStateI2C),
+ VMSTATE_UINT8(loc_sel, TPMStateI2C),
+ VMSTATE_UINT8(csum_enable, TPMStateI2C),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+/*
+ * Set data value. The i2cst->offset is not updated as called in
+ * the read path.
+ */
+static void tpm_tis_i2c_set_data(TPMStateI2C *i2cst, uint32_t data)
+{
+ i2cst->data[1] = data;
+ i2cst->data[2] = data >> 8;
+ i2cst->data[3] = data >> 16;
+ i2cst->data[4] = data >> 24;
+}
+/*
+ * Generate interface capability based on what is returned by TIS and what is
+ * expected by I2C. Save the capability in the data array overwriting the TIS
+ * capability.
+ */
+static uint32_t tpm_tis_i2c_interface_capability(TPMStateI2C *i2cst,
+ uint32_t tis_cap)
+{
+ uint32_t i2c_cap;
+
+ /* Now generate i2c capability */
+ i2c_cap = (TPM_I2C_CAP_INTERFACE_TYPE |
+ TPM_I2C_CAP_INTERFACE_VER |
+ TPM_I2C_CAP_TPM2_FAMILY |
+ TPM_I2C_CAP_LOCALITY_CAP |
+ TPM_I2C_CAP_BUS_SPEED |
+ TPM_I2C_CAP_DEV_ADDR_CHANGE);
+
+ /* Now check the TIS and set some capabilities */
+
+ /* Static burst count set */
+ if (tis_cap & TPM_TIS_CAP_BURST_COUNT_STATIC) {
+ i2c_cap |= TPM_I2C_CAP_BURST_COUNT_STATIC;
+ }
+
+ return i2c_cap;
+}
+
+/* Convert I2C register to TIS address and returns the name of the register */
+static inline void tpm_tis_i2c_to_tis_reg(TPMStateI2C *i2cst, uint8_t i2c_reg)
+{
+ const I2CRegMap *reg_map;
+ int i;
+
+ i2cst->tis_addr = 0xffffffff;
+
+ /* Special case for the STS register. */
+ if (i2c_reg >= TPM_I2C_REG_STS && i2c_reg <= TPM_I2C_REG_STS + 3) {
+ i2c_reg = TPM_I2C_REG_STS;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(tpm_tis_reg_map); i++) {
+ reg_map = &tpm_tis_reg_map[i];
+ if (reg_map->i2c_reg == i2c_reg) {
+ i2cst->reg_name = reg_map->reg_name;
+ i2cst->tis_addr = reg_map->tis_reg;
+
+ /* Include the locality in the address. */
+ assert(TPM_TIS_I2C_IS_VALID_LOCTY(i2cst->loc_sel));
+ i2cst->tis_addr += (i2cst->loc_sel << TPM_TIS_LOCALITY_SHIFT);
+ break;
+ }
+ }
+}
+
+/* Clear some fields from the structure. */
+static inline void tpm_tis_i2c_clear_data(TPMStateI2C *i2cst)
+{
+ /* Clear operation and offset */
+ i2cst->operation = 0;
+ i2cst->offset = 0;
+ i2cst->tis_addr = 0xffffffff;
+ i2cst->reg_name = NULL;
+ memset(i2cst->data, 0, sizeof(i2cst->data));
+
+ return;
+}
+
+/* Send data to TPM */
+static inline void tpm_tis_i2c_tpm_send(TPMStateI2C *i2cst)
+{
+ uint32_t data;
+ size_t offset = 0;
+ uint32_t sz = 4;
+
+ if ((i2cst->operation == OP_SEND) && (i2cst->offset > 1)) {
+
+ switch (i2cst->data[0]) {
+ case TPM_I2C_REG_DATA_CSUM_ENABLE:
+ /*
+ * Checksum is not handled by TIS code hence we will consume the
+ * register here.
+ */
+ i2cst->csum_enable = i2cst->data[1] & TPM_DATA_CSUM_ENABLED;
+ break;
+ case TPM_I2C_REG_DATA_FIFO:
+ /* Handled in the main i2c_send function */
+ break;
+ case TPM_I2C_REG_LOC_SEL:
+ /*
+ * This register is not handled by TIS so save the locality
+ * locally
+ */
+ if (TPM_TIS_I2C_IS_VALID_LOCTY(i2cst->data[1])) {
+ i2cst->loc_sel = i2cst->data[1];
+ }
+ break;
+ default:
+ /* We handle non-FIFO here */
+
+ /* Index 0 is a register. Convert byte stream to uint32_t */
+ data = i2cst->data[1];
+ data |= i2cst->data[2] << 8;
+ data |= i2cst->data[3] << 16;
+ data |= i2cst->data[4] << 24;
+
+ /* Add register specific masking */
+ switch (i2cst->data[0]) {
+ case TPM_I2C_REG_INT_ENABLE:
+ data &= TPM_I2C_INT_ENABLE_MASK;
+ break;
+ case TPM_I2C_REG_STS ... TPM_I2C_REG_STS + 3:
+ /*
+ * STS register has 4 bytes data.
+ * As per the specs following writes must be allowed.
+ * - From base address 1 to 4 bytes are allowed.
+ * - Single byte write to first or last byte must
+ * be allowed.
+ */
+ offset = i2cst->data[0] - TPM_I2C_REG_STS;
+ if (offset > 0) {
+ sz = 1;
+ }
+ data &= (TPM_I2C_STS_WRITE_MASK >> (offset * 8));
+ break;
+ }
+
+ tpm_tis_write_data(&i2cst->state, i2cst->tis_addr + offset, data,
+ sz);
+ break;
+ }
+
+ tpm_tis_i2c_clear_data(i2cst);
+ }
+
+ return;
+}
+
+/* Callback from TPM to indicate that response is copied */
+static void tpm_tis_i2c_request_completed(TPMIf *ti, int ret)
+{
+ TPMStateI2C *i2cst = TPM_TIS_I2C(ti);
+ TPMState *s = &i2cst->state;
+
+ /* Inform the common code. */
+ tpm_tis_request_completed(s, ret);
+}
+
+static enum TPMVersion tpm_tis_i2c_get_tpm_version(TPMIf *ti)
+{
+ TPMStateI2C *i2cst = TPM_TIS_I2C(ti);
+ TPMState *s = &i2cst->state;
+
+ return tpm_tis_get_tpm_version(s);
+}
+
+static int tpm_tis_i2c_event(I2CSlave *i2c, enum i2c_event event)
+{
+ TPMStateI2C *i2cst = TPM_TIS_I2C(i2c);
+ int ret = 0;
+
+ switch (event) {
+ case I2C_START_RECV:
+ trace_tpm_tis_i2c_event("START_RECV");
+ break;
+ case I2C_START_SEND:
+ trace_tpm_tis_i2c_event("START_SEND");
+ tpm_tis_i2c_clear_data(i2cst);
+ break;
+ case I2C_FINISH:
+ trace_tpm_tis_i2c_event("FINISH");
+ if (i2cst->operation == OP_SEND) {
+ tpm_tis_i2c_tpm_send(i2cst);
+ } else {
+ tpm_tis_i2c_clear_data(i2cst);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * If data is for FIFO then it is received from tpm_tis_common buffer
+ * otherwise it will be handled using single call to common code and
+ * cached in the local buffer.
+ */
+static uint8_t tpm_tis_i2c_recv(I2CSlave *i2c)
+{
+ int ret = 0;
+ uint32_t data_read;
+ TPMStateI2C *i2cst = TPM_TIS_I2C(i2c);
+ TPMState *s = &i2cst->state;
+ uint16_t i2c_reg = i2cst->data[0];
+ size_t offset;
+
+ if (i2cst->operation == OP_RECV) {
+
+ /* Do not cache FIFO data. */
+ if (i2cst->data[0] == TPM_I2C_REG_DATA_FIFO) {
+ data_read = tpm_tis_read_data(s, i2cst->tis_addr, 1);
+ ret = (data_read & 0xff);
+ } else if (i2cst->offset < sizeof(i2cst->data)) {
+ ret = i2cst->data[i2cst->offset++];
+ }
+
+ } else if ((i2cst->operation == OP_SEND) && (i2cst->offset < 2)) {
+ /* First receive call after send */
+
+ i2cst->operation = OP_RECV;
+
+ switch (i2c_reg) {
+ case TPM_I2C_REG_LOC_SEL:
+ /* Location selection register is managed by i2c */
+ tpm_tis_i2c_set_data(i2cst, i2cst->loc_sel);
+ break;
+ case TPM_I2C_REG_DATA_FIFO:
+ /* FIFO data is directly read from TPM TIS */
+ data_read = tpm_tis_read_data(s, i2cst->tis_addr, 1);
+ tpm_tis_i2c_set_data(i2cst, (data_read & 0xff));
+ break;
+ case TPM_I2C_REG_DATA_CSUM_ENABLE:
+ tpm_tis_i2c_set_data(i2cst, i2cst->csum_enable);
+ break;
+ case TPM_I2C_REG_INT_CAPABILITY:
+ /*
+ * Interrupt is not supported in the linux kernel hence we cannot
+ * test this model with interrupts.
+ */
+ tpm_tis_i2c_set_data(i2cst, TPM_I2C_INT_ENABLE_MASK);
+ break;
+ case TPM_I2C_REG_DATA_CSUM_GET:
+ /*
+ * Checksum registers are not supported by common code hence
+ * call a common code to get the checksum.
+ */
+ data_read = tpm_tis_get_checksum(s);
+
+ /* Save the byte stream in data field */
+ tpm_tis_i2c_set_data(i2cst, data_read);
+ break;
+ default:
+ data_read = tpm_tis_read_data(s, i2cst->tis_addr, 4);
+
+ switch (i2c_reg) {
+ case TPM_I2C_REG_INTF_CAPABILITY:
+ /* Prepare the capabilities as per I2C interface */
+ data_read = tpm_tis_i2c_interface_capability(i2cst,
+ data_read);
+ break;
+ case TPM_I2C_REG_STS ... TPM_I2C_REG_STS + 3:
+ offset = i2c_reg - TPM_I2C_REG_STS;
+ /*
+ * As per specs, STS bit 31:26 are reserved and must
+ * be set to 0
+ */
+ data_read &= TPM_I2C_STS_READ_MASK;
+ /*
+ * STS register has 4 bytes data.
+ * As per the specs following reads must be allowed.
+ * - From base address 1 to 4 bytes are allowed.
+ * - Last byte must be allowed to read as a single byte
+ * - Second and third byte must be allowed to read as two
+ * two bytes.
+ */
+ data_read >>= (offset * 8);
+ break;
+ }
+
+ /* Save byte stream in data[] */
+ tpm_tis_i2c_set_data(i2cst, data_read);
+ break;
+ }
+
+ /* Return first byte with this call */
+ i2cst->offset = 1; /* keep the register value intact for debug */
+ ret = i2cst->data[i2cst->offset++];
+ } else {
+ i2cst->operation = OP_RECV;
+ }
+
+ trace_tpm_tis_i2c_recv(ret);
+
+ return ret;
+}
+
+/*
+ * Send function only remembers data in the buffer and then calls
+ * TPM TIS common code during FINISH event.
+ */
+static int tpm_tis_i2c_send(I2CSlave *i2c, uint8_t data)
+{
+ TPMStateI2C *i2cst = TPM_TIS_I2C(i2c);
+
+ /* Reject non-supported registers. */
+ if (i2cst->offset == 0) {
+ /* Convert I2C register to TIS register */
+ tpm_tis_i2c_to_tis_reg(i2cst, data);
+ if (i2cst->tis_addr == 0xffffffff) {
+ return 0xffffffff;
+ }
+
+ trace_tpm_tis_i2c_send_reg(i2cst->reg_name, data);
+
+ /* We do not support device address change */
+ if (data == TPM_I2C_REG_I2C_DEV_ADDRESS) {
+ qemu_log_mask(LOG_UNIMP, "%s: Device address change "
+ "is not supported.\n", __func__);
+ return 0xffffffff;
+ }
+ } else {
+ trace_tpm_tis_i2c_send(data);
+ }
+
+ if (i2cst->offset < sizeof(i2cst->data)) {
+ i2cst->operation = OP_SEND;
+
+ /*
+ * In two cases, we save values in the local buffer.
+ * 1) The first value is always a register.
+ * 2) In case of non-FIFO multibyte registers, TIS expects full
+ * register value hence I2C layer cache the register value and send
+ * to TIS during FINISH event.
+ */
+ if ((i2cst->offset == 0) ||
+ (i2cst->data[0] != TPM_I2C_REG_DATA_FIFO)) {
+ i2cst->data[i2cst->offset++] = data;
+ } else {
+ /*
+ * The TIS can process FIFO data one byte at a time hence the FIFO
+ * data is sent to TIS directly.
+ */
+ tpm_tis_write_data(&i2cst->state, i2cst->tis_addr, data, 1);
+ }
+
+ return 0;
+ }
+
+ /* Return non-zero to indicate NAK */
+ return 1;
+}
+
+static Property tpm_tis_i2c_properties[] = {
+ DEFINE_PROP_TPMBE("tpmdev", TPMStateI2C, state.be_driver),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void tpm_tis_i2c_realizefn(DeviceState *dev, Error **errp)
+{
+ TPMStateI2C *i2cst = TPM_TIS_I2C(dev);
+ TPMState *s = &i2cst->state;
+
+ if (!tpm_find()) {
+ error_setg(errp, "at most one TPM device is permitted");
+ return;
+ }
+
+ /*
+ * Get the backend pointer. It is not initialized propery during
+ * device_class_set_props
+ */
+ s->be_driver = qemu_find_tpm_be("tpm0");
+
+ if (!s->be_driver) {
+ error_setg(errp, "'tpmdev' property is required");
+ return;
+ }
+}
+
+static void tpm_tis_i2c_reset(DeviceState *dev)
+{
+ TPMStateI2C *i2cst = TPM_TIS_I2C(dev);
+ TPMState *s = &i2cst->state;
+
+ tpm_tis_i2c_clear_data(i2cst);
+
+ i2cst->csum_enable = 0;
+ i2cst->loc_sel = 0x00;
+
+ return tpm_tis_reset(s);
+}
+
+static void tpm_tis_i2c_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+ TPMIfClass *tc = TPM_IF_CLASS(klass);
+
+ dc->realize = tpm_tis_i2c_realizefn;
+ dc->reset = tpm_tis_i2c_reset;
+ dc->vmsd = &vmstate_tpm_tis_i2c;
+ device_class_set_props(dc, tpm_tis_i2c_properties);
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+ k->event = tpm_tis_i2c_event;
+ k->recv = tpm_tis_i2c_recv;
+ k->send = tpm_tis_i2c_send;
+
+ tc->model = TPM_MODEL_TPM_TIS;
+ tc->request_completed = tpm_tis_i2c_request_completed;
+ tc->get_version = tpm_tis_i2c_get_tpm_version;
+}
+
+static const TypeInfo tpm_tis_i2c_info = {
+ .name = TYPE_TPM_TIS_I2C,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(TPMStateI2C),
+ .class_init = tpm_tis_i2c_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_TPM_IF },
+ { }
+ }
+};
+
+static void tpm_tis_i2c_register_types(void)
+{
+ type_register_static(&tpm_tis_i2c_info);
+}
+
+type_init(tpm_tis_i2c_register_types)
diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events
index f17110458e..fa882dfefe 100644
--- a/hw/tpm/trace-events
+++ b/hw/tpm/trace-events
@@ -36,3 +36,9 @@ tpm_spapr_do_crq_unknown_msg_type(uint8_t type) "Unknown message type 0x%02x"
tpm_spapr_do_crq_unknown_crq(uint8_t raw1, uint8_t raw2) "unknown CRQ 0x%02x 0x%02x ..."
tpm_spapr_post_load(void) "Delivering TPM response after resume"
tpm_spapr_caught_response(uint32_t v) "Caught response to deliver after resume: %u bytes"
+
+# tpm_tis_i2c.c
+tpm_tis_i2c_recv(uint8_t data) "TPM I2C read: 0x%X"
+tpm_tis_i2c_send(uint8_t data) "TPM I2C write: 0x%X"
+tpm_tis_i2c_event(const char *event) "TPM I2C event: %s"
+tpm_tis_i2c_send_reg(const char *name, int reg) "TPM I2C write register: %s(0x%X)"
diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h
index fb40e30ff6..66e3b45f30 100644
--- a/include/sysemu/tpm.h
+++ b/include/sysemu/tpm.h
@@ -48,6 +48,7 @@ struct TPMIfClass {
#define TYPE_TPM_TIS_SYSBUS "tpm-tis-device"
#define TYPE_TPM_CRB "tpm-crb"
#define TYPE_TPM_SPAPR "tpm-spapr"
+#define TYPE_TPM_TIS_I2C "tpm-tis-i2c"
#define TPM_IS_TIS_ISA(chr) \
object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_ISA)
@@ -57,6 +58,8 @@ struct TPMIfClass {
object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB)
#define TPM_IS_SPAPR(chr) \
object_dynamic_cast(OBJECT(chr), TYPE_TPM_SPAPR)
+#define TPM_IS_TIS_I2C(chr) \
+ object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_I2C)
/* returns NULL unless there is exactly one TPM device */
static inline TPMIf *tpm_find(void)
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 4/7] tests/avocado/aspeed: Add TPM TIS I2C test
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
` (2 preceding siblings ...)
2023-04-20 12:32 ` [PULL 3/7] tpm: Add support for TPM device over I2C bus Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-20 12:32 ` [PULL 5/7] qtest: Add functions for accessing devices on Aspeed I2C controller Stefan Berger
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Joel Stanley, Stefan Berger, Cédric Le Goater,
Ninad Palsule
From: Joel Stanley <joel@jms.id.au>
Add a new buildroot image based test that attaches a TPM emulator to the
I2C bus and checks for a known PCR0 value for the image that was booted.
Note that this does not tear down swtpm process when qemu execution fails.
The swtpm process will exit when qemu exits if a connection has been
made, but if the test errors before connection then the swtpm process
will still be around.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>
Message-id: 20230328120844.190914-1-joel@jms.id.au
---
tests/avocado/machine_aspeed.py | 42 +++++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index d2c57ccb7e..2b532c4834 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -7,14 +7,18 @@
import time
import os
+import tempfile
+import subprocess
from avocado_qemu import QemuSystemTest
from avocado_qemu import wait_for_console_pattern
from avocado_qemu import exec_command
from avocado_qemu import exec_command_and_wait_for_pattern
from avocado_qemu import interrupt_interactive_console_until_pattern
+from avocado_qemu import has_cmd
from avocado.utils import archive
from avocado import skipIf
+from avocado import skipUnless
class AST1030Machine(QemuSystemTest):
@@ -132,7 +136,7 @@ def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
self.do_test_arm_aspeed(image_path)
- def do_test_arm_aspeed_buildroot_start(self, image, cpu_id):
+ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
self.require_netdev('user')
self.vm.set_console()
@@ -146,7 +150,7 @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id):
self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id)
self.wait_for_console_pattern('lease of 10.0.2.15')
# the line before login:
- self.wait_for_console_pattern('Aspeed EVB')
+ self.wait_for_console_pattern(pattern)
time.sleep(0.1)
exec_command(self, 'root')
time.sleep(0.1)
@@ -229,6 +233,40 @@ def test_arm_ast2600_evb_buildroot(self):
'0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
self.do_test_arm_aspeed_buildroot_poweroff()
+ @skipUnless(*has_cmd('swtpm'))
+ def test_arm_ast2600_evb_buildroot_tpm(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:ast2600-evb
+ """
+
+ image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+ 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img')
+ image_hash = ('a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
+ image_path = self.fetch_asset(image_url, asset_hash=image_hash,
+ algorithm='sha256')
+
+ socket = os.path.join(self.vm.sock_dir, 'swtpm-socket')
+
+ subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
+ '--tpmstate', f'dir={self.vm.temp_dir}',
+ '--ctrl', f'type=unixio,path={socket}'])
+
+ self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}')
+ self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm')
+ self.vm.add_args('-device',
+ 'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
+ self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
+ exec_command(self, "passw0rd")
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
+ 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/tpm/tpm0/pcr-sha256/0',
+ 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0');
+
+ self.do_test_arm_aspeed_buildroot_poweroff()
class AST2x00MachineSDK(QemuSystemTest):
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 5/7] qtest: Add functions for accessing devices on Aspeed I2C controller
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
` (3 preceding siblings ...)
2023-04-20 12:32 ` [PULL 4/7] tests/avocado/aspeed: Add TPM TIS I2C test Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-20 12:32 ` [PULL 6/7] qtest: Move tpm_util_tis_transmit() into tpm-tis-utils.c and rename it Stefan Berger
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Stefan Berger, Cédric Le Goater,
Ninad Palsule, Thomas Huth
Add read and write functions for accessing registers of I2C devices
connected to the Aspeed I2C controller.
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230331173051.3857801-2-stefanb@linux.ibm.com
---
include/hw/i2c/aspeed_i2c.h | 7 +++
tests/qtest/qtest_aspeed.c | 117 ++++++++++++++++++++++++++++++++++++
tests/qtest/qtest_aspeed.h | 41 +++++++++++++
3 files changed, 165 insertions(+)
create mode 100644 tests/qtest/qtest_aspeed.c
create mode 100644 tests/qtest/qtest_aspeed.h
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index adc904d6c1..51c944efea 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -38,6 +38,13 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
#define ASPEED_I2C_OLD_NUM_REG 11
#define ASPEED_I2C_NEW_NUM_REG 22
+#define A_I2CD_M_STOP_CMD BIT(5)
+#define A_I2CD_M_RX_CMD BIT(3)
+#define A_I2CD_M_TX_CMD BIT(1)
+#define A_I2CD_M_START_CMD BIT(0)
+
+#define A_I2CD_MASTER_EN BIT(0)
+
/* Tx State Machine */
#define I2CD_TX_STATE_MASK 0xf
#define I2CD_IDLE 0x0
diff --git a/tests/qtest/qtest_aspeed.c b/tests/qtest/qtest_aspeed.c
new file mode 100644
index 0000000000..f6da9adea9
--- /dev/null
+++ b/tests/qtest/qtest_aspeed.c
@@ -0,0 +1,117 @@
+/*
+ * Aspeed i2c bus interface for reading from and writing to i2c device registers
+ *
+ * Copyright (c) 2023 IBM Corporation
+ *
+ * Authors:
+ * Stefan Berger <stefanb@linux.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include "qtest_aspeed.h"
+#include "hw/i2c/aspeed_i2c.h"
+
+static void aspeed_i2c_startup(QTestState *s, uint32_t baseaddr,
+ uint8_t slave_addr, uint8_t reg)
+{
+ uint32_t v;
+ static int once;
+
+ if (!once) {
+ /* one time: enable master */
+ qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, 0);
+ v = qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN;
+ qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, v);
+ once = 1;
+ }
+
+ /* select device */
+ qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1);
+ qtest_writel(s, baseaddr + A_I2CD_CMD,
+ A_I2CD_M_START_CMD | A_I2CD_M_RX_CMD);
+
+ /* select the register to write to */
+ qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg);
+ qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
+}
+
+static uint32_t aspeed_i2c_read_n(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, size_t nbytes)
+{
+ uint32_t res = 0;
+ uint32_t v;
+ size_t i;
+
+ aspeed_i2c_startup(s, baseaddr, slave_addr, reg);
+
+ for (i = 0; i < nbytes; i++) {
+ qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD);
+ v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8;
+ res |= (v & 0xff) << (i * 8);
+ }
+
+ qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
+
+ return res;
+}
+
+uint32_t aspeed_i2c_readl(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
+{
+ return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint32_t));
+}
+
+uint16_t aspeed_i2c_readw(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
+{
+ return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint16_t));
+}
+
+uint8_t aspeed_i2c_readb(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
+{
+ return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint8_t));
+}
+
+static void aspeed_i2c_write_n(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint32_t v, size_t nbytes)
+{
+ size_t i;
+
+ aspeed_i2c_startup(s, baseaddr, slave_addr, reg);
+
+ for (i = 0; i < nbytes; i++) {
+ qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, v & 0xff);
+ v >>= 8;
+ qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
+ }
+
+ qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
+}
+
+void aspeed_i2c_writel(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint32_t v)
+{
+ aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
+}
+
+void aspeed_i2c_writew(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint16_t v)
+{
+ aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
+}
+
+void aspeed_i2c_writeb(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint8_t v)
+{
+ aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
+}
diff --git a/tests/qtest/qtest_aspeed.h b/tests/qtest/qtest_aspeed.h
new file mode 100644
index 0000000000..235dfaa186
--- /dev/null
+++ b/tests/qtest/qtest_aspeed.h
@@ -0,0 +1,41 @@
+/*
+ * Aspeed i2c bus interface to reading and writing to i2c device registers
+ *
+ * Copyright (c) 2023 IBM Corporation
+ *
+ * Authors:
+ * Stefan Berger <stefanb@linux.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef QTEST_ASPEED_H
+#define QTEST_ASPEED_H
+
+#include <stdint.h>
+
+#include "libqtest.h"
+
+#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
+
+/* Implements only AST2600 I2C controller */
+
+static inline uint32_t ast2600_i2c_calc_bus_addr(uint8_t bus_num)
+{
+ return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
+}
+
+uint8_t aspeed_i2c_readb(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
+uint16_t aspeed_i2c_readw(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
+uint32_t aspeed_i2c_readl(QTestState *s,
+ uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
+void aspeed_i2c_writeb(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint8_t v);
+void aspeed_i2c_writew(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint16_t v);
+void aspeed_i2c_writel(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint32_t v);
+
+#endif
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 6/7] qtest: Move tpm_util_tis_transmit() into tpm-tis-utils.c and rename it
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
` (4 preceding siblings ...)
2023-04-20 12:32 ` [PULL 5/7] qtest: Add functions for accessing devices on Aspeed I2C controller Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-20 12:32 ` [PULL 7/7] qtest: Add a test case for TPM TIS I2C connected to Aspeed I2C controller Stefan Berger
2023-04-22 4:28 ` [PULL 0/7] Merge tpm 2023/04/20 v1 Richard Henderson
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Stefan Berger, Ninad Palsule, Thomas Huth
To be able to remove tpm_tis_base_addr from test cases that do not really
need it move the tpm_util_tis_transmit() function into tpm-tis-utils.c and
rename it to tpm_tis_transmit().
Fix a locality parameter in a test case on the way.
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230331173051.3857801-3-stefanb@linux.ibm.com
---
tests/qtest/tpm-crb-swtpm-test.c | 3 --
tests/qtest/tpm-crb-test.c | 3 --
tests/qtest/tpm-tis-device-swtpm-test.c | 5 +--
tests/qtest/tpm-tis-swtpm-test.c | 5 +--
tests/qtest/tpm-tis-util.c | 47 ++++++++++++++++++++++++-
tests/qtest/tpm-tis-util.h | 4 +++
tests/qtest/tpm-util.c | 45 -----------------------
tests/qtest/tpm-util.h | 3 --
8 files changed, 56 insertions(+), 59 deletions(-)
diff --git a/tests/qtest/tpm-crb-swtpm-test.c b/tests/qtest/tpm-crb-swtpm-test.c
index 40254f762f..ffeb1c396b 100644
--- a/tests/qtest/tpm-crb-swtpm-test.c
+++ b/tests/qtest/tpm-crb-swtpm-test.c
@@ -19,9 +19,6 @@
#include "tpm-tests.h"
#include "hw/acpi/tpm.h"
-/* Not used but needed for linking */
-uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE;
-
typedef struct TestState {
char *src_tpm_path;
char *dst_tpm_path;
diff --git a/tests/qtest/tpm-crb-test.c b/tests/qtest/tpm-crb-test.c
index 7b94453390..396ae3f91c 100644
--- a/tests/qtest/tpm-crb-test.c
+++ b/tests/qtest/tpm-crb-test.c
@@ -19,9 +19,6 @@
#include "qemu/module.h"
#include "tpm-emu.h"
-/* Not used but needed for linking */
-uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE;
-
#define TPM_CMD "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00"
static void tpm_crb_test(const void *data)
diff --git a/tests/qtest/tpm-tis-device-swtpm-test.c b/tests/qtest/tpm-tis-device-swtpm-test.c
index 8c067fddd4..517a077005 100644
--- a/tests/qtest/tpm-tis-device-swtpm-test.c
+++ b/tests/qtest/tpm-tis-device-swtpm-test.c
@@ -18,6 +18,7 @@
#include "libqtest.h"
#include "qemu/module.h"
#include "tpm-tests.h"
+#include "tpm-tis-util.h"
#include "hw/acpi/tpm.h"
uint64_t tpm_tis_base_addr = 0xc000000;
@@ -33,7 +34,7 @@ static void tpm_tis_swtpm_test(const void *data)
{
const TestState *ts = data;
- tpm_test_swtpm_test(ts->src_tpm_path, tpm_util_tis_transfer,
+ tpm_test_swtpm_test(ts->src_tpm_path, tpm_tis_transfer,
"tpm-tis-device", MACHINE_OPTIONS);
}
@@ -42,7 +43,7 @@ static void tpm_tis_swtpm_migration_test(const void *data)
const TestState *ts = data;
tpm_test_swtpm_migration_test(ts->src_tpm_path, ts->dst_tpm_path, ts->uri,
- tpm_util_tis_transfer, "tpm-tis-device",
+ tpm_tis_transfer, "tpm-tis-device",
MACHINE_OPTIONS);
}
diff --git a/tests/qtest/tpm-tis-swtpm-test.c b/tests/qtest/tpm-tis-swtpm-test.c
index 11539c0a52..105e42e21d 100644
--- a/tests/qtest/tpm-tis-swtpm-test.c
+++ b/tests/qtest/tpm-tis-swtpm-test.c
@@ -17,6 +17,7 @@
#include "libqtest.h"
#include "qemu/module.h"
#include "tpm-tests.h"
+#include "tpm-tis-util.h"
#include "hw/acpi/tpm.h"
uint64_t tpm_tis_base_addr = TPM_TIS_ADDR_BASE;
@@ -31,7 +32,7 @@ static void tpm_tis_swtpm_test(const void *data)
{
const TestState *ts = data;
- tpm_test_swtpm_test(ts->src_tpm_path, tpm_util_tis_transfer,
+ tpm_test_swtpm_test(ts->src_tpm_path, tpm_tis_transfer,
"tpm-tis", NULL);
}
@@ -40,7 +41,7 @@ static void tpm_tis_swtpm_migration_test(const void *data)
const TestState *ts = data;
tpm_test_swtpm_migration_test(ts->src_tpm_path, ts->dst_tpm_path, ts->uri,
- tpm_util_tis_transfer, "tpm-tis", NULL);
+ tpm_tis_transfer, "tpm-tis", NULL);
}
int main(int argc, char **argv)
diff --git a/tests/qtest/tpm-tis-util.c b/tests/qtest/tpm-tis-util.c
index 939893bf01..728cd3e065 100644
--- a/tests/qtest/tpm-tis-util.c
+++ b/tests/qtest/tpm-tis-util.c
@@ -52,7 +52,7 @@ void tpm_tis_test_check_localities(const void *data)
uint32_t rid;
for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES; locty++) {
- access = readb(TIS_REG(0, TPM_TIS_REG_ACCESS));
+ access = readb(TIS_REG(locty, TPM_TIS_REG_ACCESS));
g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
@@ -449,3 +449,48 @@ void tpm_tis_test_check_transmit(const void *data)
writeb(TIS_REG(0, TPM_TIS_REG_ACCESS), TPM_TIS_ACCESS_ACTIVE_LOCALITY);
access = readb(TIS_REG(0, TPM_TIS_REG_ACCESS));
}
+
+void tpm_tis_transfer(QTestState *s,
+ const unsigned char *req, size_t req_size,
+ unsigned char *rsp, size_t rsp_size)
+{
+ uint32_t sts;
+ uint16_t bcount;
+ size_t i;
+
+ /* request use of locality 0 */
+ qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_ACCESS), TPM_TIS_ACCESS_REQUEST_USE);
+ qtest_writel(s, TIS_REG(0, TPM_TIS_REG_STS), TPM_TIS_STS_COMMAND_READY);
+
+ sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS));
+ bcount = (sts >> 8) & 0xffff;
+ g_assert_cmpint(bcount, >=, req_size);
+
+ /* transmit command */
+ for (i = 0; i < req_size; i++) {
+ qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_DATA_FIFO), req[i]);
+ }
+
+ /* start processing */
+ qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_STS), TPM_TIS_STS_TPM_GO);
+
+ uint64_t end_time = g_get_monotonic_time() + 50 * G_TIME_SPAN_SECOND;
+ do {
+ sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS));
+ if ((sts & TPM_TIS_STS_DATA_AVAILABLE) != 0) {
+ break;
+ }
+ } while (g_get_monotonic_time() < end_time);
+
+ sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS));
+ bcount = (sts >> 8) & 0xffff;
+
+ memset(rsp, 0, rsp_size);
+ for (i = 0; i < bcount; i++) {
+ rsp[i] = qtest_readb(s, TIS_REG(0, TPM_TIS_REG_DATA_FIFO));
+ }
+
+ /* relinquish use of locality 0 */
+ qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_ACCESS),
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+}
diff --git a/tests/qtest/tpm-tis-util.h b/tests/qtest/tpm-tis-util.h
index d10efe86ae..03910a7ba7 100644
--- a/tests/qtest/tpm-tis-util.h
+++ b/tests/qtest/tpm-tis-util.h
@@ -20,4 +20,8 @@ void tpm_tis_test_check_access_reg_seize(const void *data);
void tpm_tis_test_check_access_reg_release(const void *data);
void tpm_tis_test_check_transmit(const void *data);
+void tpm_tis_transfer(QTestState *s,
+ const unsigned char *req, size_t req_size,
+ unsigned char *rsp, size_t rsp_size);
+
#endif /* TESTS_TPM_TIS_UTIL_H */
diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c
index a7efe2d0d2..1c0319e6e7 100644
--- a/tests/qtest/tpm-util.c
+++ b/tests/qtest/tpm-util.c
@@ -51,51 +51,6 @@ void tpm_util_crb_transfer(QTestState *s,
qtest_memread(s, raddr, rsp, rsp_size);
}
-void tpm_util_tis_transfer(QTestState *s,
- const unsigned char *req, size_t req_size,
- unsigned char *rsp, size_t rsp_size)
-{
- uint32_t sts;
- uint16_t bcount;
- size_t i;
-
- /* request use of locality 0 */
- qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_ACCESS), TPM_TIS_ACCESS_REQUEST_USE);
- qtest_writel(s, TIS_REG(0, TPM_TIS_REG_STS), TPM_TIS_STS_COMMAND_READY);
-
- sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS));
- bcount = (sts >> 8) & 0xffff;
- g_assert_cmpint(bcount, >=, req_size);
-
- /* transmit command */
- for (i = 0; i < req_size; i++) {
- qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_DATA_FIFO), req[i]);
- }
-
- /* start processing */
- qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_STS), TPM_TIS_STS_TPM_GO);
-
- uint64_t end_time = g_get_monotonic_time() + 50 * G_TIME_SPAN_SECOND;
- do {
- sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS));
- if ((sts & TPM_TIS_STS_DATA_AVAILABLE) != 0) {
- break;
- }
- } while (g_get_monotonic_time() < end_time);
-
- sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS));
- bcount = (sts >> 8) & 0xffff;
-
- memset(rsp, 0, rsp_size);
- for (i = 0; i < bcount; i++) {
- rsp[i] = qtest_readb(s, TIS_REG(0, TPM_TIS_REG_DATA_FIFO));
- }
-
- /* relinquish use of locality 0 */
- qtest_writeb(s, TIS_REG(0, TPM_TIS_REG_ACCESS),
- TPM_TIS_ACCESS_ACTIVE_LOCALITY);
-}
-
void tpm_util_startup(QTestState *s, tx_func *tx)
{
unsigned char buffer[1024];
diff --git a/tests/qtest/tpm-util.h b/tests/qtest/tpm-util.h
index 80720afac0..0cb28dd6e5 100644
--- a/tests/qtest/tpm-util.h
+++ b/tests/qtest/tpm-util.h
@@ -27,9 +27,6 @@ typedef void (tx_func)(QTestState *s,
void tpm_util_crb_transfer(QTestState *s,
const unsigned char *req, size_t req_size,
unsigned char *rsp, size_t rsp_size);
-void tpm_util_tis_transfer(QTestState *s,
- const unsigned char *req, size_t req_size,
- unsigned char *rsp, size_t rsp_size);
void tpm_util_startup(QTestState *s, tx_func *tx);
void tpm_util_pcrextend(QTestState *s, tx_func *tx);
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 7/7] qtest: Add a test case for TPM TIS I2C connected to Aspeed I2C controller
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
` (5 preceding siblings ...)
2023-04-20 12:32 ` [PULL 6/7] qtest: Move tpm_util_tis_transmit() into tpm-tis-utils.c and rename it Stefan Berger
@ 2023-04-20 12:32 ` Stefan Berger
2023-04-22 4:28 ` [PULL 0/7] Merge tpm 2023/04/20 v1 Richard Henderson
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Berger @ 2023-04-20 12:32 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Stefan Berger, Cédric Le Goater,
Ninad Palsule
Add a test case for the TPM TIS I2C device exercising most of its
functionality, including localities.
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Ninad Palsule<ninad@linux.ibm.com>
Message-id: 20230331173051.3857801-4-stefanb@linux.ibm.com
---
tests/qtest/meson.build | 3 +
tests/qtest/tpm-tis-i2c-test.c | 663 +++++++++++++++++++++++++++++++++
2 files changed, 666 insertions(+)
create mode 100644 tests/qtest/tpm-tis-i2c-test.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 85ea4e8d99..cfc66ade6f 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -200,6 +200,7 @@ qtests_arm = \
(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
(config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
['arm-cpu-features',
'microbit-test',
'test-arm-mptimer',
@@ -212,6 +213,7 @@ qtests_aarch64 = \
['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
['arm-cpu-features',
'numa-test',
'boot-serial-test',
@@ -304,6 +306,7 @@ qtests = {
'tpm-crb-test': [io, tpmemu_files],
'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'],
+ 'tpm-tis-i2c-test': [io, tpmemu_files, 'qtest_aspeed.c'],
'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'],
'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
diff --git a/tests/qtest/tpm-tis-i2c-test.c b/tests/qtest/tpm-tis-i2c-test.c
new file mode 100644
index 0000000000..7a590ac551
--- /dev/null
+++ b/tests/qtest/tpm-tis-i2c-test.c
@@ -0,0 +1,663 @@
+/*
+ * QTest testcases for TPM TIS on I2C (derived from TPM TIS test)
+ *
+ * Copyright (c) 2023 IBM Corporation
+ * Copyright (c) 2023 Red Hat, Inc.
+ *
+ * Authors:
+ * Stefan Berger <stefanb@linux.ibm.com>
+ * Marc-André Lureau <marcandre.lureau@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include <glib/gstdio.h>
+
+#include "libqtest-single.h"
+#include "hw/acpi/tpm.h"
+#include "hw/pci/pci_ids.h"
+#include "qtest_aspeed.h"
+#include "tpm-emu.h"
+
+#define DEBUG_TIS_TEST 0
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_TIS_TEST) { \
+ printf(fmt, ## __VA_ARGS__); \
+ } \
+} while (0)
+
+#define DPRINTF_ACCESS \
+ DPRINTF("%s: %d: locty=%d l=%d access=0x%02x pending_request_flag=0x%x\n", \
+ __func__, __LINE__, locty, l, access, pending_request_flag)
+
+#define DPRINTF_STS \
+ DPRINTF("%s: %d: sts = 0x%08x\n", __func__, __LINE__, sts)
+
+#define I2C_SLAVE_ADDR 0x2e
+#define I2C_DEV_BUS_NUM 10
+
+static const uint8_t TPM_CMD[12] =
+ "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00";
+
+static uint32_t aspeed_bus_addr;
+
+static uint8_t cur_locty = 0xff;
+
+static void tpm_tis_i2c_set_locty(uint8_t locty)
+{
+ if (cur_locty != locty) {
+ cur_locty = locty;
+ aspeed_i2c_writeb(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR,
+ TPM_I2C_REG_LOC_SEL, locty);
+ }
+}
+
+static uint8_t tpm_tis_i2c_readb(uint8_t locty, uint8_t reg)
+{
+ tpm_tis_i2c_set_locty(locty);
+ return aspeed_i2c_readb(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg);
+}
+
+static uint16_t tpm_tis_i2c_readw(uint8_t locty, uint8_t reg)
+{
+ tpm_tis_i2c_set_locty(locty);
+ return aspeed_i2c_readw(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg);
+}
+
+static uint32_t tpm_tis_i2c_readl(uint8_t locty, uint8_t reg)
+{
+ tpm_tis_i2c_set_locty(locty);
+ return aspeed_i2c_readl(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg);
+}
+
+static void tpm_tis_i2c_writeb(uint8_t locty, uint8_t reg, uint8_t v)
+{
+ if (reg != TPM_I2C_REG_LOC_SEL) {
+ tpm_tis_i2c_set_locty(locty);
+ }
+ aspeed_i2c_writeb(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg, v);
+}
+
+static void tpm_tis_i2c_writel(uint8_t locty, uint8_t reg, uint32_t v)
+{
+ if (reg != TPM_I2C_REG_LOC_SEL) {
+ tpm_tis_i2c_set_locty(locty);
+ }
+ aspeed_i2c_writel(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg, v);
+}
+
+static void tpm_tis_i2c_test_basic(const void *data)
+{
+ uint8_t access;
+ uint32_t v, v2;
+
+ /*
+ * All register accesses below must work without locality 0 being the
+ * active locality. Therefore, ensure access is released.
+ */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+ access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* read interrupt capability -- none are supported */
+ v = tpm_tis_i2c_readl(0, TPM_I2C_REG_INT_CAPABILITY);
+ g_assert_cmpint(v, ==, 0);
+
+ /* try to enable all interrupts */
+ tpm_tis_i2c_writel(0, TPM_I2C_REG_INT_ENABLE, 0xffffffff);
+ v = tpm_tis_i2c_readl(0, TPM_I2C_REG_INT_ENABLE);
+ /* none could be enabled */
+ g_assert_cmpint(v, ==, 0);
+
+ /* enable csum */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_CSUM_ENABLE, TPM_DATA_CSUM_ENABLED);
+ /* check csum enable register has bit 0 set */
+ v = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
+ g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
+ /* reading it as 32bit register returns same result */
+ v = tpm_tis_i2c_readl(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
+ g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
+
+ /* disable csum */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_CSUM_ENABLE, 0);
+ /* check csum enable register has bit 0 clear */
+ v = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
+ g_assert_cmpint(v, ==, 0);
+
+ /* write to unsupported register '1' */
+ tpm_tis_i2c_writel(0, 1, 0x12345678);
+ v = tpm_tis_i2c_readl(0, 1);
+ g_assert_cmpint(v, ==, 0xffffffff);
+
+ /* request use of locality */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE);
+
+ /* read byte from STS + 3 */
+ v = tpm_tis_i2c_readb(0, TPM_I2C_REG_STS + 3);
+ g_assert_cmpint(v, ==, 0);
+
+ /* check STS after writing to STS + 3 */
+ v = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_STS + 3, 0xf);
+ v2 = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ g_assert_cmpint(v, ==, v2);
+
+ /* release access */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+
+ /* select locality 5 -- must not be possible */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_LOC_SEL, 5);
+ v = tpm_tis_i2c_readb(0, TPM_I2C_REG_LOC_SEL);
+ g_assert_cmpint(v, ==, 0);
+}
+
+static void tpm_tis_i2c_test_check_localities(const void *data)
+{
+ uint8_t locty, l;
+ uint8_t access;
+ uint32_t capability, i2c_cap;
+ uint32_t didvid;
+ uint32_t rid;
+
+ for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES; locty++) {
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ capability = tpm_tis_i2c_readl(locty, TPM_I2C_REG_INTF_CAPABILITY);
+ i2c_cap = (TPM_I2C_CAP_INTERFACE_TYPE |
+ TPM_I2C_CAP_INTERFACE_VER |
+ TPM_I2C_CAP_TPM2_FAMILY |
+ TPM_I2C_CAP_LOCALITY_CAP |
+ TPM_I2C_CAP_BUS_SPEED |
+ TPM_I2C_CAP_DEV_ADDR_CHANGE);
+ g_assert_cmpint(capability, ==, i2c_cap);
+
+ didvid = tpm_tis_i2c_readl(locty, TPM_I2C_REG_DID_VID);
+ g_assert_cmpint(didvid, ==, (1 << 16) | PCI_VENDOR_ID_IBM);
+
+ rid = tpm_tis_i2c_readl(locty, TPM_I2C_REG_RID);
+ g_assert_cmpint(rid, !=, 0);
+ g_assert_cmpint(rid, !=, 0xffffffff);
+
+ /* locality selection must be at locty */
+ l = tpm_tis_i2c_readb(locty, TPM_I2C_REG_LOC_SEL);
+ g_assert_cmpint(l, ==, locty);
+ }
+}
+
+static void tpm_tis_i2c_test_check_access_reg(const void *data)
+{
+ uint8_t locty;
+ uint8_t access;
+
+ /* do not test locality 4 (hw only) */
+ for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES - 1; locty++) {
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* request use of locality */
+ tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_REQUEST_USE);
+
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* release access */
+ tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+ }
+}
+
+/*
+ * Test case for seizing access by a higher number locality
+ */
+static void tpm_tis_i2c_test_check_access_reg_seize(const void *data)
+{
+ int locty, l;
+ uint8_t access;
+ uint8_t pending_request_flag;
+
+ /* do not test locality 4 (hw only) */
+ for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES - 1; locty++) {
+ pending_request_flag = 0;
+
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* request use of locality */
+ tpm_tis_i2c_writeb(locty,
+ TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE);
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* lower localities cannot seize access */
+ for (l = 0; l < locty; l++) {
+ /* lower locality is not active */
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* try to request use from 'l' */
+ tpm_tis_i2c_writeb(l,
+ TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_REQUEST_USE);
+
+ /*
+ * requesting use from 'l' was not possible;
+ * we must see REQUEST_USE and possibly PENDING_REQUEST
+ */
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_REQUEST_USE |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /*
+ * locality 'locty' must be unchanged;
+ * we must see PENDING_REQUEST
+ */
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_PENDING_REQUEST |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* try to seize from 'l' */
+ tpm_tis_i2c_writeb(l,
+ TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_SEIZE);
+ /* seize from 'l' was not possible */
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_REQUEST_USE |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* locality 'locty' must be unchanged */
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_PENDING_REQUEST |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /*
+ * on the next loop we will have a PENDING_REQUEST flag
+ * set for locality 'l'
+ */
+ pending_request_flag = TPM_TIS_ACCESS_PENDING_REQUEST;
+ }
+
+ /*
+ * higher localities can 'seize' access but not 'request use';
+ * note: this will activate first l+1, then l+2 etc.
+ */
+ for (l = locty + 1; l < TPM_TIS_NUM_LOCALITIES - 1; l++) {
+ /* try to 'request use' from 'l' */
+ tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_REQUEST_USE);
+
+ /*
+ * requesting use from 'l' was not possible; we should see
+ * REQUEST_USE and may see PENDING_REQUEST
+ */
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_REQUEST_USE |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /*
+ * locality 'l-1' must be unchanged; we should always
+ * see PENDING_REQUEST from 'l' requesting access
+ */
+ access = tpm_tis_i2c_readb(l - 1, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_PENDING_REQUEST |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* try to seize from 'l' */
+ tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_SEIZE);
+
+ /* seize from 'l' was possible */
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* l - 1 should show that it has BEEN_SEIZED */
+ access = tpm_tis_i2c_readb(l - 1, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_BEEN_SEIZED |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* clear the BEEN_SEIZED flag and make sure it's gone */
+ tpm_tis_i2c_writeb(l - 1, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_BEEN_SEIZED);
+
+ access = tpm_tis_i2c_readb(l - 1, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+ }
+
+ /*
+ * PENDING_REQUEST will not be set if locty = 0 since all localities
+ * were active; in case of locty = 1, locality 0 will be active
+ * but no PENDING_REQUEST anywhere
+ */
+ if (locty <= 1) {
+ pending_request_flag = 0;
+ }
+
+ /* release access from l - 1; this activates locty - 1 */
+ l--;
+
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+
+ DPRINTF("%s: %d: relinquishing control on l = %d\n",
+ __func__, __LINE__, l);
+ tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ for (l = locty - 1; l >= 0; l--) {
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* release this locality */
+ tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+
+ if (l == 1) {
+ pending_request_flag = 0;
+ }
+ }
+
+ /* no locality may be active now */
+ for (l = 0; l < TPM_TIS_NUM_LOCALITIES - 1; l++) {
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+ }
+ }
+}
+
+/*
+ * Test case for getting access when higher number locality relinquishes access
+ */
+static void tpm_tis_i2c_test_check_access_reg_release(const void *data)
+{
+ int locty, l;
+ uint8_t access;
+ uint8_t pending_request_flag;
+
+ /* do not test locality 4 (hw only) */
+ for (locty = TPM_TIS_NUM_LOCALITIES - 2; locty >= 0; locty--) {
+ pending_request_flag = 0;
+
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* request use of locality */
+ tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_REQUEST_USE);
+ access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ /* request use of all other localities */
+ for (l = 0; l < TPM_TIS_NUM_LOCALITIES - 1; l++) {
+ if (l == locty) {
+ continue;
+ }
+ /*
+ * request use of locality 'l' -- we MUST see REQUEST USE and
+ * may see PENDING_REQUEST
+ */
+ tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_REQUEST_USE);
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_REQUEST_USE |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+ pending_request_flag = TPM_TIS_ACCESS_PENDING_REQUEST;
+ }
+ /* release locality 'locty' */
+ tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+ /*
+ * highest locality should now be active; release it and make sure the
+ * next higest locality is active afterwards
+ */
+ for (l = TPM_TIS_NUM_LOCALITIES - 2; l >= 0; l--) {
+ if (l == locty) {
+ continue;
+ }
+ /* 'l' should be active now */
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+ /* 'l' relinquishes access */
+ tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+ access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
+ DPRINTF_ACCESS;
+ if (l == 1 || (locty <= 1 && l == 2)) {
+ pending_request_flag = 0;
+ }
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ pending_request_flag |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+ }
+ }
+}
+
+/*
+ * Test case for transmitting packets
+ */
+static void tpm_tis_i2c_test_check_transmit(const void *data)
+{
+ const TPMTestState *s = data;
+ uint8_t access;
+ uint32_t sts, v;
+ uint16_t bcount, csum, bcount2;
+ size_t i;
+
+ /* enable csum */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_CSUM_ENABLE, TPM_DATA_CSUM_ENABLED);
+ /* check csum enable register has bit 0 set */
+ v = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
+ g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
+ /* reading it as 32bit register returns same result */
+ v = tpm_tis_i2c_readl(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
+ g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
+
+ /* request use of locality 0 */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE);
+ access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS);
+ g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
+ TPM_TIS_ACCESS_ACTIVE_LOCALITY |
+ TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
+
+ sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ DPRINTF_STS;
+
+ g_assert_cmpint(sts & 0xff, ==, 0);
+
+ bcount = (sts >> 8) & 0xffff;
+ g_assert_cmpint(bcount, >=, 128);
+
+ /* read bcount from STS + 1 must work also */
+ bcount2 = tpm_tis_i2c_readw(0, TPM_I2C_REG_STS + 1);
+ g_assert_cmpint(bcount, ==, bcount2);
+
+ /* ic2 must have bits 26-31 zero */
+ g_assert_cmpint(sts & (0x1f << 26), ==, 0);
+
+ tpm_tis_i2c_writel(0, TPM_I2C_REG_STS, TPM_TIS_STS_COMMAND_READY);
+ sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ DPRINTF_STS;
+ g_assert_cmpint(sts & 0xff, ==, TPM_TIS_STS_COMMAND_READY);
+
+ /* transmit command */
+ for (i = 0; i < sizeof(TPM_CMD); i++) {
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_FIFO, TPM_CMD[i]);
+ sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ DPRINTF_STS;
+ if (i < sizeof(TPM_CMD) - 1) {
+ g_assert_cmpint(sts & 0xff, ==,
+ TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID);
+ } else {
+ g_assert_cmpint(sts & 0xff, ==, TPM_TIS_STS_VALID);
+ }
+ g_assert_cmpint((sts >> 8) & 0xffff, ==, --bcount);
+ }
+ /* read the checksum */
+ csum = tpm_tis_i2c_readw(0, TPM_I2C_REG_DATA_CSUM_GET);
+ g_assert_cmpint(csum, ==, 0x6733);
+
+ /* start processing */
+ tpm_tis_i2c_writeb(0, TPM_I2C_REG_STS, TPM_TIS_STS_TPM_GO);
+
+ uint64_t end_time = g_get_monotonic_time() + 50 * G_TIME_SPAN_SECOND;
+ do {
+ sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ if ((sts & TPM_TIS_STS_DATA_AVAILABLE) != 0) {
+ break;
+ }
+ } while (g_get_monotonic_time() < end_time);
+
+ sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ DPRINTF_STS;
+ g_assert_cmpint(sts & 0xff, == ,
+ TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE);
+ bcount = (sts >> 8) & 0xffff;
+
+ /* read response */
+ uint8_t tpm_msg[sizeof(struct tpm_hdr)];
+ g_assert_cmpint(sizeof(tpm_msg), ==, bcount);
+
+ for (i = 0; i < sizeof(tpm_msg); i++) {
+ tpm_msg[i] = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_FIFO);
+ sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
+ DPRINTF_STS;
+ if (sts & TPM_TIS_STS_DATA_AVAILABLE) {
+ g_assert_cmpint((sts >> 8) & 0xffff, ==, --bcount);
+ }
+ }
+ g_assert_cmpmem(tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_msg));
+
+ /* relinquish use of locality 0 */
+ tpm_tis_i2c_writeb(0,
+ TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_ACTIVE_LOCALITY);
+ access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+ char *args;
+ char *tmp_path = g_dir_make_tmp("qemu-tpm-tis-i2c-test.XXXXXX", NULL);
+ GThread *thread;
+ TPMTestState test;
+
+ module_call_init(MODULE_INIT_QOM);
+ g_test_init(&argc, &argv, NULL);
+
+ test.addr = g_new0(SocketAddress, 1);
+ test.addr->type = SOCKET_ADDRESS_TYPE_UNIX;
+ test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL);
+ g_mutex_init(&test.data_mutex);
+ g_cond_init(&test.data_cond);
+ test.data_cond_signal = false;
+ test.tpm_version = TPM_VERSION_2_0;
+
+ thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test);
+ tpm_emu_test_wait_cond(&test);
+
+ aspeed_bus_addr = ast2600_i2c_calc_bus_addr(I2C_DEV_BUS_NUM);
+
+ args = g_strdup_printf(
+ "-machine rainier-bmc -accel tcg "
+ "-chardev socket,id=chr,path=%s "
+ "-tpmdev emulator,id=tpm0,chardev=chr "
+ "-device tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.%d,address=0x%x",
+ test.addr->u.q_unix.path,
+ I2C_DEV_BUS_NUM,
+ I2C_SLAVE_ADDR);
+ qtest_start(args);
+
+ qtest_add_data_func("/tpm-tis-i2c/test_basic", &test,
+ tpm_tis_i2c_test_basic);
+
+ qtest_add_data_func("/tpm-tis-i2c/test_check_localities", &test,
+ tpm_tis_i2c_test_check_localities);
+
+ qtest_add_data_func("/tpm-tis-i2c/check_access_reg", &test,
+ tpm_tis_i2c_test_check_access_reg);
+
+ qtest_add_data_func("/tpm-tis-i2c/check_access_reg_seize", &test,
+ tpm_tis_i2c_test_check_access_reg_seize);
+
+ qtest_add_data_func("/tpm-tis-i2c/check_access_reg_release", &test,
+ tpm_tis_i2c_test_check_access_reg_release);
+
+ qtest_add_data_func("/tpm-tis-i2c/test_check_transmit", &test,
+ tpm_tis_i2c_test_check_transmit);
+
+ ret = g_test_run();
+
+ qtest_end();
+
+ g_thread_join(thread);
+ g_unlink(test.addr->u.q_unix.path);
+ qapi_free_SocketAddress(test.addr);
+ g_rmdir(tmp_path);
+ g_free(tmp_path);
+ g_free(args);
+ return ret;
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PULL 0/7] Merge tpm 2023/04/20 v1
2023-04-20 12:32 [PULL 0/7] Merge tpm 2023/04/20 v1 Stefan Berger
` (6 preceding siblings ...)
2023-04-20 12:32 ` [PULL 7/7] qtest: Add a test case for TPM TIS I2C connected to Aspeed I2C controller Stefan Berger
@ 2023-04-22 4:28 ` Richard Henderson
7 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2023-04-22 4:28 UTC (permalink / raw)
To: Stefan Berger, qemu-devel; +Cc: peter.maydell
On 4/20/23 13:32, Stefan Berger wrote:
> Hello!
>
> This series provides TPM I2C device model support along with test cases.
>
> Regards,
> Stefan
>
> The following changes since commit 2d82c32b2ceaca3dc3da5e36e10976f34bfcb598:
>
> Open 8.1 development tree (2023-04-20 10:05:25 +0100)
>
> are available in the Git repository at:
>
> https://github.com/stefanberger/qemu-tpm.git tags/pull-tpm-2023-04-20-1
>
> for you to fetch changes up to 9d81aa3c0fe7480d722517f69e1bcb4aeaaf859c:
>
> qtest: Add a test case for TPM TIS I2C connected to Aspeed I2C controller (2023-04-20 08:17:15 -0400)
>
>
> Joel Stanley (1):
> tests/avocado/aspeed: Add TPM TIS I2C test
>
> Ninad Palsule (3):
> docs: Add support for TPM devices over I2C bus
> tpm: Extend common APIs to support TPM TIS I2C
> tpm: Add support for TPM device over I2C bus
>
> Stefan Berger (3):
> qtest: Add functions for accessing devices on Aspeed I2C controller
> qtest: Move tpm_util_tis_transmit() into tpm-tis-utils.c and rename it
> qtest: Add a test case for TPM TIS I2C connected to Aspeed I2C
> controller
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 9+ messages in thread