From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, "Michael S . Tsirkin" <mst@redhat.com>
Cc: "Fan Ni" <fan.ni@samsung.com>,
linuxarm@huawei.com, "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Gregory Price" <gourry.memverge@gmail.com>,
"Mike Maslenkin" <mike.maslenkin@gmail.com>,
"Dave Jiang" <dave.jiang@intel.com>,
linux-cxl@vger.kernel.org
Subject: [PATCH v5 2/3] hw/mem: Use memory_region_size() in cxl_type3
Date: Fri, 21 Apr 2023 17:08:26 +0100 [thread overview]
Message-ID: <20230421160827.2227-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230421160827.2227-1-Jonathan.Cameron@huawei.com>
Accessors prefered over direct use of int128_get64() as they
clamp out of range values. None are expected here but
cleaner to always use the accessor than mix and match.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v5: New patch to tidy up existing instance before adding more of
them.
- Use memory_region_size() to access the size of memory regions.
We may eventually need to allow for larger addresses but it
is unlikely to be a problem any time soon.
---
hw/mem/cxl_type3.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 1bd5963a3f..2db756851c 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -52,7 +52,7 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
.DSMADhandle = dsmad_handle,
.flags = CDAT_DSMAS_FLAG_NV,
.DPA_base = 0,
- .DPA_length = int128_get64(mr->size),
+ .DPA_length = memory_region_size(mr),
};
/* For now, no memory side cache, plausiblish numbers */
@@ -133,7 +133,7 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
/* Reserved - the non volatile from DSMAS matters */
.EFI_memory_type_attr = 2,
.DPA_offset = 0,
- .DPA_length = int128_get64(mr->size),
+ .DPA_length = memory_region_size(mr),
};
/* Header always at start of structure */
@@ -698,7 +698,7 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
return MEMTX_ERROR;
}
- if (dpa_offset > int128_get64(mr->size)) {
+ if (dpa_offset > memory_region_size(mr)) {
return MEMTX_ERROR;
}
@@ -721,7 +721,7 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
return MEMTX_OK;
}
- if (dpa_offset > int128_get64(mr->size)) {
+ if (dpa_offset > memory_region_size(mr)) {
return MEMTX_OK;
}
return address_space_write(&ct3d->hostmem_as, dpa_offset, attrs,
--
2.37.2
next prev parent reply other threads:[~2023-04-21 16:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 16:08 [PATCH v5 0/3] hw/mem: CXL Type-3 Volatile Memory Support Jonathan Cameron via
2023-04-21 16:08 ` [PATCH v5 1/3] tests/qtest/cxl-test: whitespace, line ending cleanup Jonathan Cameron via
2023-04-21 16:08 ` Jonathan Cameron via [this message]
2023-05-16 5:22 ` [PATCH v5 2/3] hw/mem: Use memory_region_size() in cxl_type3 Gregory Price
2023-04-21 16:08 ` [PATCH v5 3/3] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) Jonathan Cameron via
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