qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
	qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name,
	jiaxun.yang@flygoat.com, philmd@linaro.org,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [PATCH v3 01/57] include/exec/memop: Add bits describing atomicity
Date: Tue, 25 Apr 2023 20:30:50 +0100	[thread overview]
Message-ID: <20230425193146.2106111-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230425193146.2106111-1-richard.henderson@linaro.org>

These bits may be used to describe the precise atomicity
requirements of the guest, which may then be used to
constrain the methods by which it may be emulated by the host.

For instance, the AArch64 LDP (32-bit) instruction changes
semantics with ARMv8.4 LSE2, from

  MO_64 | MO_ATMAX_4 | MO_ATOM_IFALIGN
  (64-bits, single-copy atomic only on 4 byte units,
   nonatomic if not aligned by 4),

to

  MO_64 | MO_ATMAX_SIZE | MO_ATOM_WITHIN16
  (64-bits, single-copy atomic within a 16 byte block)

The former may be implemented with two 4 byte loads, or
a single 8 byte load if that happens to be efficient on
the host.  The latter may not, and may also require a
helper when misaligned.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/memop.h | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/include/exec/memop.h b/include/exec/memop.h
index 25d027434a..04e4048f0b 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -81,6 +81,42 @@ typedef enum MemOp {
     MO_ALIGN_32 = 5 << MO_ASHIFT,
     MO_ALIGN_64 = 6 << MO_ASHIFT,
 
+    /*
+     * MO_ATOM_* describes that atomicity requirements of the operation:
+     * MO_ATOM_IFALIGN: the operation must be single-copy atomic if and
+     *    only if it is aligned; if unaligned there is no atomicity.
+     * MO_ATOM_NONE: the operation has no atomicity requirements.
+     * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts
+     *    by the alignment.  E.g. if the address is 0 mod 4, then each
+     *    4-byte subobject is single-copy atomic.
+     *    This is the atomicity of IBM Power and S390X processors.
+     * MO_ATOM_WITHIN16: the operation is single-copy atomic, even if it
+     *    is unaligned, so long as it does not cross a 16-byte boundary;
+     *    if it crosses a 16-byte boundary there is no atomicity.
+     *    This is the atomicity of Arm FEAT_LSE2.
+     *
+     * MO_ATMAX_* describes the maximum atomicity unit required:
+     * MO_ATMAX_SIZE: the entire operation, i.e. MO_SIZE.
+     * MO_ATMAX_[248]: units of N bytes.
+     *
+     * Note the default (i.e. 0) values are single-copy atomic to the
+     * size of the operation, if aligned.  This retains the behaviour
+     * from before these were introduced.
+     */
+    MO_ATOM_SHIFT    = 8,
+    MO_ATOM_MASK     = 0x3 << MO_ATOM_SHIFT,
+    MO_ATOM_IFALIGN  = 0 << MO_ATOM_SHIFT,
+    MO_ATOM_NONE     = 1 << MO_ATOM_SHIFT,
+    MO_ATOM_SUBALIGN = 2 << MO_ATOM_SHIFT,
+    MO_ATOM_WITHIN16 = 3 << MO_ATOM_SHIFT,
+
+    MO_ATMAX_SHIFT = 10,
+    MO_ATMAX_MASK  = 0x3 << MO_ATMAX_SHIFT,
+    MO_ATMAX_SIZE  = 0 << MO_ATMAX_SHIFT,
+    MO_ATMAX_2     = 1 << MO_ATMAX_SHIFT,
+    MO_ATMAX_4     = 2 << MO_ATMAX_SHIFT,
+    MO_ATMAX_8     = 3 << MO_ATMAX_SHIFT,
+
     /* Combinations of the above, for ease of use.  */
     MO_UB    = MO_8,
     MO_UW    = MO_16,
-- 
2.34.1



  reply	other threads:[~2023-04-25 19:42 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-25 19:30 [PATCH v3 00/57] tcg: Improve atomicity support Richard Henderson
2023-04-25 19:30 ` Richard Henderson [this message]
2023-04-25 19:30 ` [PATCH v3 02/57] accel/tcg: Add cpu_in_serial_context Richard Henderson
2023-05-04 14:52   ` Peter Maydell
2023-04-25 19:30 ` [PATCH v3 03/57] accel/tcg: Introduce tlb_read_idx Richard Henderson
2023-04-25 19:30 ` [PATCH v3 04/57] accel/tcg: Reorg system mode load helpers Richard Henderson
2023-04-25 19:30 ` [PATCH v3 05/57] accel/tcg: Reorg system mode store helpers Richard Henderson
2023-04-25 19:30 ` [PATCH v3 06/57] accel/tcg: Honor atomicity of loads Richard Henderson
2023-04-25 19:30 ` [PATCH v3 07/57] accel/tcg: Honor atomicity of stores Richard Henderson
2023-04-25 19:30 ` [PATCH v3 08/57] target/loongarch: Do not include tcg-ldst.h Richard Henderson
2023-04-26  0:45   ` Song Gao
2023-04-25 19:30 ` [PATCH v3 09/57] tcg: Unify helper_{be,le}_{ld,st}* Richard Henderson
2023-04-25 19:30 ` [PATCH v3 10/57] accel/tcg: Implement helper_{ld, st}*_mmu for user-only Richard Henderson
2023-04-25 19:31 ` [PATCH v3 11/57] tcg/tci: Use helper_{ld,st}*_mmu " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 12/57] tcg: Add 128-bit guest memory primitives Richard Henderson
2023-04-25 19:31 ` [PATCH v3 13/57] meson: Detect atomic128 support with optimization Richard Henderson
2023-04-25 19:31 ` [PATCH v3 14/57] tcg/i386: Add have_atomic16 Richard Henderson
2023-04-25 19:31 ` [PATCH v3 15/57] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc Richard Henderson
2023-04-25 19:31 ` [PATCH v3 16/57] accel/tcg: Add aarch64 specific support in ldst_atomicity Richard Henderson
2023-04-25 19:31 ` [PATCH v3 17/57] tcg/aarch64: Detect have_lse, have_lse2 for linux Richard Henderson
2023-04-25 19:31 ` [PATCH v3 18/57] tcg/aarch64: Detect have_lse, have_lse2 for darwin Richard Henderson
2023-04-25 19:31 ` [PATCH v3 19/57] accel/tcg: Add have_lse2 support in ldst_atomicity Richard Henderson
2023-04-25 19:31 ` [PATCH v3 20/57] tcg: Introduce TCG_OPF_TYPE_MASK Richard Henderson
2023-04-25 19:31 ` [PATCH v3 21/57] tcg/i386: Use full load/store helpers in user-only mode Richard Henderson
2023-04-25 19:31 ` [PATCH v3 22/57] tcg/aarch64: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 23/57] tcg/ppc: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 24/57] tcg/loongarch64: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 25/57] tcg/riscv: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 26/57] tcg/arm: Adjust constraints on qemu_ld/st Richard Henderson
2023-04-25 19:31 ` [PATCH v3 27/57] tcg/arm: Use full load/store helpers in user-only mode Richard Henderson
2023-04-25 19:31 ` [PATCH v3 28/57] tcg/mips: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 29/57] tcg/s390x: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 30/57] tcg/sparc64: Allocate %g2 as a third temporary Richard Henderson
2023-04-25 19:31 ` [PATCH v3 31/57] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13 Richard Henderson
2023-04-25 19:31 ` [PATCH v3 32/57] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32 Richard Henderson
2023-04-25 19:31 ` [PATCH v3 33/57] tcg/sparc64: Split out tcg_out_movi_s32 Richard Henderson
2023-04-25 19:31 ` [PATCH v3 34/57] tcg/sparc64: Use standard slow path for softmmu Richard Henderson
2023-04-25 19:31 ` [PATCH v3 35/57] accel/tcg: Remove helper_unaligned_{ld,st} Richard Henderson
2023-04-25 19:31 ` [PATCH v3 36/57] tcg/loongarch64: Assert the host supports unaligned accesses Richard Henderson
2023-04-25 19:31 ` [PATCH v3 37/57] tcg/loongarch64: Support softmmu " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 38/57] tcg/riscv: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 39/57] tcg: Introduce tcg_target_has_memory_bswap Richard Henderson
2023-04-25 19:31 ` [PATCH v3 40/57] tcg: Add INDEX_op_qemu_{ld,st}_i128 Richard Henderson
2023-04-25 19:31 ` [PATCH v3 41/57] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret} Richard Henderson
2023-04-25 19:31 ` [PATCH v3 42/57] tcg: Introduce atom_and_align_for_opc Richard Henderson
2023-04-25 19:31 ` [PATCH v3 43/57] tcg/i386: Use atom_and_align_for_opc Richard Henderson
2023-04-25 19:31 ` [PATCH v3 44/57] tcg/aarch64: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 45/57] tcg/arm: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 46/57] tcg/loongarch64: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 47/57] tcg/mips: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 48/57] tcg/ppc: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 49/57] tcg/riscv: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 50/57] tcg/s390x: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 51/57] tcg/sparc64: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 52/57] tcg/i386: Honor 64-bit atomicity in 32-bit mode Richard Henderson
2023-04-25 19:31 ` [PATCH v3 53/57] tcg/i386: Support 128-bit load/store with have_atomic16 Richard Henderson
2023-04-25 19:31 ` [PATCH v3 54/57] tcg/aarch64: Rename temporaries Richard Henderson
2023-04-25 19:31 ` [PATCH v3 55/57] tcg/aarch64: Support 128-bit load/store Richard Henderson
2023-04-25 19:31 ` [PATCH v3 56/57] tcg/ppc: " Richard Henderson
2023-04-25 19:31 ` [PATCH v3 57/57] tcg/s390x: " Richard Henderson
2023-05-02 16:11 ` [PATCH v3 00/57] tcg: Improve atomicity support Peter Maydell
2023-05-02 19:19   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230425193146.2106111-2-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=git@xen0n.name \
    --cc=jiaxun.yang@flygoat.com \
    --cc=philmd@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=qemu-s390x@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).