From: Drew Fustini <dfustini@baylibre.com>
To: "Ved Shanbhogue" <ved@rivosinc.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Weiwei Li" <liweiwei@iscas.ac.cn>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Nicolas Pitre" <npitre@baylibre.com>,
"Adrien Ricciardi" <aricciardi@baylibre.com>,
"Kornel Dulęba" <mindal@semihalf.com>
Cc: Drew Fustini <dfustini@baylibre.com>
Subject: [RFC PATCH v2 7/9] hw/riscv: add CBQRI controllers to virt machine
Date: Tue, 25 Apr 2023 13:38:32 -0700 [thread overview]
Message-ID: <20230425203834.1135306-8-dfustini@baylibre.com> (raw)
In-Reply-To: <20230425203834.1135306-1-dfustini@baylibre.com>
From: Nicolas Pitre <npitre@baylibre.com>
Add CBQRI controllers to the RISC-V virt machine. The device properties
can be fully configured from the command line:
$ qemu-system-riscv64 -M virt ... \
-device riscv.cbqri.capacity,mmio_base=0x04828000[,...]
-device riscv.cbqri.bandwidth,mmio_base=0x04829000[,...]
The mmio_base option is mandatory, the others are optional.
Many -device arguments as wanted can be provided as long as their
mmio regions don't conflict.
To see all possible options:
$ qemu-system-riscv64 -device riscv.cbqri.capacity,help
riscv.cbqri.capacity options:
alloc_op_config_limit=<bool> - (default: true)
alloc_op_flush_rcid=<bool> - (default: true)
alloc_op_read_limit=<bool> - (default: true)
at_code=<bool> - (default: true)
at_data=<bool> - (default: true)
max_mcids=<uint16> - (default: 256)
max_rcids=<uint16> - (default: 64)
mmio_base=<uint64> - (default: 0)
mon_evt_id_none=<bool> - (default: true)
mon_evt_id_occupancy=<bool> - (default: true)
mon_op_config_event=<bool> - (default: true)
mon_op_read_counter=<bool> - (default: true)
ncblks=<uint16> - (default: 16)
target=<str>
$ qemu-system-riscv64 -device riscv.cbqri.bandwidth,help
riscv.cbqri.bandwidth options:
alloc_op_config_limit=<bool> - (default: true)
alloc_op_read_limit=<bool> - (default: true)
at_code=<bool> - (default: true)
at_data=<bool> - (default: true)
max_mcids=<uint16> - (default: 256)
max_rcids=<uint16> - (default: 64)
mmio_base=<uint64> - (default: 0)
mon_evt_id_none=<bool> - (default: true)
mon_evt_id_rdonly_count=<bool> - (default: true)
mon_evt_id_rdwr_count=<bool> - (default: true)
mon_evt_id_wronly_count=<bool> - (default: true)
mon_op_config_event=<bool> - (default: true)
mon_op_read_counter=<bool> - (default: true)
nbwblks=<uint16> - (default: 1024)
target=<str>
Boolean options correspond to hardware capabilities that can be disabled
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
Changes since v1:
- remove initialization of the example SoC now that device properties
can be use to configure controllers from the command line
hw/riscv/virt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4e3efbee16f0..674a6a34de3a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -50,6 +50,7 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
#include "hw/acpi/aml-build.h"
+#include "hw/riscv/cbqri.h"
#include "qapi/qapi-visit-common.h"
/*
@@ -1688,6 +1689,8 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TPM
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
#endif
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RISCV_CBQRI_BC);
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RISCV_CBQRI_CC);
object_class_property_add_bool(oc, "aclint", virt_get_aclint,
virt_set_aclint);
--
2.34.1
next prev parent reply other threads:[~2023-04-25 20:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-25 20:38 [RFC PATCH v2 0/9] riscv: implement Ssqosid extension and CBQRI controllers Drew Fustini
2023-04-25 20:38 ` [RFC PATCH v2 1/9] riscv: implement Ssqosid extension and sqoscfg CSR Drew Fustini
2023-04-26 7:35 ` Weiwei Li
2023-04-25 20:38 ` [RFC PATCH v2 2/9] hw/riscv: define capabilities of CBQRI controllers Drew Fustini
2023-04-25 20:38 ` [RFC PATCH v2 3/9] hw/riscv: implement CBQRI capacity controller Drew Fustini
2023-04-25 20:38 ` [RFC PATCH v2 4/9] hw/riscv: implement CBQRI bandwidth controller Drew Fustini
2023-04-25 20:38 ` [RFC PATCH v2 5/9] hw/riscv: Kconfig: add CBQRI options Drew Fustini
2023-04-25 20:38 ` [RFC PATCH v2 6/9] hw/riscv: meson: add CBQRI controllers to the build Drew Fustini
2023-04-25 20:38 ` Drew Fustini [this message]
2023-04-25 20:38 ` [RFC PATCH v2 8/9] hw/riscv: instantiate CBQRI controllers for an example SoC Drew Fustini
2023-04-25 20:38 ` [RFC PATCH v2 9/9] hw/riscv: build example SoC when CBQRI_EXAMPLE_SOC enabled Drew Fustini
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