From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: tsimpson@quicinc.com, richard.henderson@linaro.org,
philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com,
quic_mathbern@quicinc.com
Subject: [PATCH 13/21] Hexagon (target/hexagon) Short-circuit packet HVX writes
Date: Tue, 25 Apr 2023 17:42:28 -0700 [thread overview]
Message-ID: <20230426004234.1319401-4-tsimpson@quicinc.com> (raw)
In-Reply-To: <20230426004234.1319401-1-tsimpson@quicinc.com>
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/genptr.c | 6 ++++-
target/hexagon/translate.c | 46 +++++++++++++++++++++++++++++++++++++-
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index da68d19ed3..8e5afab931 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -1101,7 +1101,11 @@ static void gen_log_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int num,
static intptr_t get_result_qreg(DisasContext *ctx, int qnum)
{
- return offsetof(CPUHexagonState, future_QRegs[qnum]);
+ if (ctx->need_commit) {
+ return offsetof(CPUHexagonState, future_QRegs[qnum]);
+ } else {
+ return offsetof(CPUHexagonState, QRegs[qnum]);
+ }
}
static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 07ed36f6a8..8e024b2cd2 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -70,6 +70,10 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
{
intptr_t offset;
+ if (!ctx->need_commit) {
+ return offsetof(CPUHexagonState, VRegs[regnum]);
+ }
+
/* See if it is already allocated */
for (int i = 0; i < ctx->future_vregs_idx; i++) {
if (ctx->future_vregs_num[i] == regnum) {
@@ -374,7 +378,7 @@ static bool need_commit(DisasContext *ctx)
return true;
}
- if (pkt->num_insns == 1) {
+ if (pkt->num_insns == 1 && !pkt->pkt_has_hvx) {
return false;
}
@@ -394,6 +398,40 @@ static bool need_commit(DisasContext *ctx)
}
}
+ /* Check for overlap between HVX reads and writes */
+ for (int i = 0; i < ctx->vreg_log_idx; i++) {
+ int vnum = ctx->vreg_log[i];
+ if (test_bit(vnum, ctx->vregs_read)) {
+ return true;
+ }
+ }
+ if (!bitmap_empty(ctx->vregs_updated_tmp, NUM_VREGS)) {
+ int i = find_first_bit(ctx->vregs_updated_tmp, NUM_VREGS);
+ while (i < NUM_VREGS) {
+ if (test_bit(i, ctx->vregs_read)) {
+ return true;
+ }
+ i = find_next_bit(ctx->vregs_updated_tmp, NUM_VREGS, i + 1);
+ }
+ }
+ if (!bitmap_empty(ctx->vregs_select, NUM_VREGS)) {
+ int i = find_first_bit(ctx->vregs_select, NUM_VREGS);
+ while (i < NUM_VREGS) {
+ if (test_bit(i, ctx->vregs_read)) {
+ return true;
+ }
+ i = find_next_bit(ctx->vregs_select, NUM_VREGS, i + 1);
+ }
+ }
+
+ /* Check for overlap between HVX predicate reads and writes */
+ for (int i = 0; i < ctx->qreg_log_idx; i++) {
+ int qnum = ctx->qreg_log[i];
+ if (test_bit(qnum, ctx->qregs_read)) {
+ return true;
+ }
+ }
+
return false;
}
@@ -787,6 +825,12 @@ static void gen_commit_hvx(DisasContext *ctx)
{
int i;
+ /* Early exit if not needed */
+ if (!ctx->need_commit) {
+ g_assert(!pkt_has_hvx_store(ctx->pkt));
+ return;
+ }
+
/*
* for (i = 0; i < ctx->vreg_log_idx; i++) {
* int rnum = ctx->vreg_log[i];
--
2.25.1
next prev parent reply other threads:[~2023-04-26 0:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 0:42 [PATCH 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis Taylor Simpson
2023-04-26 0:42 ` [PATCH 11/21] Hexagon (target/hexagon) Short-circuit packet register writes Taylor Simpson
2023-04-27 10:40 ` Richard Henderson
2023-04-26 0:42 ` [PATCH 12/21] Hexagon (target/hexagon) Short-circuit packet predicate writes Taylor Simpson
2023-04-27 10:41 ` Richard Henderson
2023-04-26 0:42 ` Taylor Simpson [this message]
2023-04-27 10:42 ` [PATCH 13/21] Hexagon (target/hexagon) Short-circuit packet HVX writes Richard Henderson
2023-04-26 0:42 ` [PATCH 14/21] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets Taylor Simpson
2023-04-27 10:44 ` Richard Henderson
2023-04-26 0:42 ` [PATCH 15/21] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns Taylor Simpson
2023-04-27 10:52 ` Richard Henderson
2023-04-26 0:42 ` [PATCH 16/21] Hexagon (target/hexagon) Make special new_value for USR Taylor Simpson
2023-04-27 10:57 ` Richard Henderson
2023-04-26 0:42 ` [PATCH 17/21] Hexagon (target/hexagon) Move new_value to DisasContext Taylor Simpson
2023-04-27 11:01 ` Richard Henderson
2023-04-27 11:03 ` Richard Henderson
2023-04-26 0:42 ` [PATCH 18/21] Hexagon (target/hexagon) Move new_pred_value " Taylor Simpson
2023-04-27 11:03 ` Richard Henderson
2023-04-26 0:42 ` [PATCH 19/21] Hexagon (target/hexagon) Move pred_written " Taylor Simpson
2023-04-27 11:05 ` Richard Henderson
2023-04-27 8:04 ` [PATCH 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis Richard Henderson
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