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From: Tong Ho <tong.ho@amd.com>
To: <qemu-arm@nongnu.org>
Cc: <qemu-devel@nongnu.org>, <alistair@alistair23.me>,
	<edgar.iglesias@gmail.comi>, <frasse.iglesias@gmail.com>,
	<peter.maydell@linaro.org>, <tong.ho@amd.com>
Subject: [PATCH] hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
Date: Wed, 26 Apr 2023 14:16:07 -0700	[thread overview]
Message-ID: <20230426211607.2054776-1-tong.ho@amd.com> (raw)

Add a check in the bit-set operation to write the backstore
only if the affected bit is 0 before.

With this in place, there will be no need for callers to
do the checking in order to avoid unnecessary writes.

Signed-off-by: Tong Ho <tong.ho@amd.com>
---
 hw/nvram/xlnx-efuse.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index fdfffaab99..655c40b8d1 100644
--- a/hw/nvram/xlnx-efuse.c
+++ b/hw/nvram/xlnx-efuse.c
@@ -143,6 +143,8 @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
 
 bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
 {
+    uint32_t set, *row;
+
     if (efuse_ro_bits_find(s, bit)) {
         g_autofree char *path = object_get_canonical_path(OBJECT(s));
 
@@ -152,8 +154,13 @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
         return false;
     }
 
-    s->fuse32[bit / 32] |= 1 << (bit % 32);
-    efuse_bdrv_sync(s, bit);
+    /* Avoid back-end write unless there is a real update */
+    row = &s->fuse32[bit / 32];
+    set = 1 << (bit % 32);
+    if (!(set & *row)) {
+        *row |= set;
+        efuse_bdrv_sync(s, bit);
+    }
     return true;
 }
 
-- 
2.25.1



             reply	other threads:[~2023-04-27  0:31 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-26 21:16 Tong Ho [this message]
2023-04-27  5:14 ` [PATCH] hw/nvram: Avoid unnecessary Xilinx eFuse backstore write Alistair Francis
2023-04-27  6:38 ` Francisco Iglesias
2023-04-28 23:08 ` Philippe Mathieu-Daudé
2023-07-17 10:06 ` Peter Maydell

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