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[217.76.87.243]) by smtp.gmail.com with ESMTPSA id r26-20020ac24d1a000000b004efecbf5768sm1842889lfi.264.2023.04.26.23.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 23:38:56 -0700 (PDT) Date: Thu, 27 Apr 2023 08:38:55 +0200 From: Francisco Iglesias To: Tong Ho Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, alistair@alistair23.me, edgar.iglesias@gmail.comi, peter.maydell@linaro.org Subject: Re: [PATCH] hw/nvram: Avoid unnecessary Xilinx eFuse backstore write Message-ID: <20230427063854.GA6030@fralle-msi> References: <20230426211607.2054776-1-tong.ho@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230426211607.2054776-1-tong.ho@amd.com> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On [2023 Apr 26] Wed 14:16:07, Tong Ho wrote: > Add a check in the bit-set operation to write the backstore > only if the affected bit is 0 before. > > With this in place, there will be no need for callers to > do the checking in order to avoid unnecessary writes. > > Signed-off-by: Tong Ho Reviewed-by: Francisco Iglesias > --- > hw/nvram/xlnx-efuse.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c > index fdfffaab99..655c40b8d1 100644 > --- a/hw/nvram/xlnx-efuse.c > +++ b/hw/nvram/xlnx-efuse.c > @@ -143,6 +143,8 @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) > > bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) > { > + uint32_t set, *row; > + > if (efuse_ro_bits_find(s, bit)) { > g_autofree char *path = object_get_canonical_path(OBJECT(s)); > > @@ -152,8 +154,13 @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) > return false; > } > > - s->fuse32[bit / 32] |= 1 << (bit % 32); > - efuse_bdrv_sync(s, bit); > + /* Avoid back-end write unless there is a real update */ > + row = &s->fuse32[bit / 32]; > + set = 1 << (bit % 32); > + if (!(set & *row)) { > + *row |= set; > + efuse_bdrv_sync(s, bit); > + } > return true; > } > > -- > 2.25.1 >