[PATCH 1/2] target: riscv: fix typos

[Yu Chien Peter Lin <peterlin@andestech.com>]

Fix a few minor typos for PMU events.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
 target/riscv/cpu.h        | 2 +-
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/pmu.c        | 8 ++++----
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..eab518542c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -812,7 +812,7 @@ enum riscv_pmu_event_idx {
     RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
     RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
     RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
-    RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
+    RISCV_PMU_EVENT_CACHE_ITLB_READ_MISS = 0x10021,
 };
 
 /* CSR function table */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f88c503cf4..5d3e032ec9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1210,7 +1210,7 @@ static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_READ_MISS;
         break;
     case MMU_DATA_LOAD:
         pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index fa1e1484c2..0be0e8027b 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -62,17 +62,17 @@ void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
    fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
    fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
 
-   /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
+   /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x01 type(0x01) */
    fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
    fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
    fdt_event_ctr_map[8] = cpu_to_be32(cmask);
 
-   /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
+   /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x01 type(0x01) */
    fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
    fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
    fdt_event_ctr_map[11] = cpu_to_be32(cmask);
 
-   /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
+   /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x01 type(0x01) */
    fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
    fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
    fdt_event_ctr_map[14] = cpu_to_be32(cmask);
@@ -317,7 +317,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
     case RISCV_PMU_EVENT_HW_INSTRUCTIONS:
     case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS:
     case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS:
-    case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS:
+    case RISCV_PMU_EVENT_CACHE_ITLB_READ_MISS:
         break;
     default:
         /* We don't support any raw events right now */
-- 
2.34.1